Xiang Wang 0e788c985c riscv: update the definition of intptr_t/uintptr_t ... These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f. Through this we know that the length of the long's bit is equal to pointer. So update this code. This's more flexible. Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27768 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2018-08-30 14:48:26 +00:00
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acpi
arch	riscv: update the definition of intptr_t/uintptr_t	2018-08-30 14:48:26 +00:00
commonlib	cbtable: remove chromeos_acpi from cbtable	2018-08-22 15:33:50 +00:00
console
cpu	cpu/intel/common: add function to init cppc_config	2018-08-20 15:53:28 +00:00
device	nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c	2018-08-21 23:04:08 +00:00
drivers	drivers/intel/gma: Fix OpRegion Mailbox3 backlight change	2018-08-30 14:45:50 +00:00
ec	acpi: Hide Chrome and coreboot specific devices	2018-08-28 15:14:42 +00:00
include	siemens/mc_apl1: Disable PCI clock outputs on XIO bridge	2018-08-27 06:31:27 +00:00
lib	lib/gpio.c: Validate num_gpio	2018-08-28 15:36:51 +00:00
mainboard	mb/google/octopus: Add missing IOstandy settings.	2018-08-30 14:47:23 +00:00
northbridge	nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled	2018-08-22 18:26:14 +00:00
security	security/tpm: Fix TPM 1.2 state machine issues	2018-08-21 15:45:15 +00:00
soc	soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()	2018-08-30 14:47:52 +00:00
southbridge	intel: Use common HPET table revision function	2018-08-27 15:50:52 +00:00
superio	superio/ite/it8721f: Add SuperIO ACPI declarations	2018-08-21 14:45:36 +00:00
vendorcode	acpi: Hide Chrome and coreboot specific devices	2018-08-28 15:14:42 +00:00
Kconfig