coreboot/src
Subrata Banik 0e2510f616 soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig
Alder Lake onwards IA SoC to select CAR_HAS_L3_PROTECTED_WAYS from SoC
Kconfig and here is modified flow as below:
Add new MSR 0xc85 IA32_L3_PROTECTED_WAYS
Update eNEM init flow:
  - Set MSR 0xC85 L3_Protected_ways = (1 << data ways) - 1
Update eNEM teardown flow:
  - Set MSR 0xC85 L3_Protected_ways = 0x00000

BUG=b:168820083
TEST=Verified filling up the entire cache with memcpy at the beginning
itself and then running the entire bootblock, verstage, debug FSP-M
without running into any issue. This proves that code caching and
eviction is working as expected in eNEM mode.

Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16 05:07:12 +00:00
..
acpi arch/x86/acpi: rename KEY_KBDILLUMTOGGLE to KEY_KBD_BKLIGHT_TOGGLE 2021-08-06 16:26:44 +00:00
arch arch/x86: smbios write 7 table using deterministic cache functions 2021-08-11 05:50:02 +00:00
commonlib util/elogtool: add tool to print elog events 2021-08-05 22:00:35 +00:00
console console/hw-debug_sink: Update for fast/slow console distinction 2021-08-04 15:15:45 +00:00
cpu cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPI 2021-07-27 14:00:32 +00:00
device device/pci_rom: Make ON_DEVICE_ROM_LOAD condition truthy 2021-07-20 16:52:35 +00:00
drivers drivers/generic/alc1015: Add HID to support alc1019 2021-08-12 17:57:55 +00:00
ec ec/google/chromeec: Add code for KEY_MICMUTE and KEY_KBD_BKLIGHT_TOGGLE 2021-08-06 16:26:51 +00:00
include soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig 2021-08-16 05:07:12 +00:00
lib Move post_codes.h to commonlib/console/ 2021-08-04 15:15:51 +00:00
mainboard mb/google/brya: set PL4 value dynamically for thermal 2021-08-15 02:07:35 +00:00
northbridge nb/intel/haswell: Move MRC glue code into a subfolder 2021-08-02 14:59:45 +00:00
security vboot/secdata_tpm: Add WRITE_STCLEAR attr to RW ARB spaces 2021-07-26 07:27:48 +00:00
soc soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS Kconfig 2021-08-16 05:07:12 +00:00
southbridge soc/amd/common/block/acpimmio: add Kconfig option for biosram accessors 2021-07-26 19:34:20 +00:00
superio src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
vendorcode vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore setting 2021-08-12 17:58:45 +00:00
Kconfig option: Allow mainboards to implement the API 2021-05-28 11:37:25 +00:00