Felix Held 0de53be394 soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ... This ports commit 8c28e51a16 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>		2023-04-28 20:13:47 +00:00
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amd	soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses	2023-04-28 20:13:47 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86
intel	soc/intel/common/block/pmc: Sort Kconfig in alphabetical order	2023-04-28 13:38:59 +00:00
mediatek	soc/mediatek/mt8183: Fix set but unused variable	2023-04-24 13:58:13 +00:00
nvidia
qualcomm	qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLib	2023-03-17 00:34:08 +00:00
rockchip
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540
ti
ucb/riscv