0d34a50a36
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific postcodes into the common postcode list, and uses it for the cache-as-RAM init as needed. Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in most of the others, the values were consolidated into 0x21. This will change the value on some platforms. Any conflicts should get sorted out later in the conversion process. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8527334e679a23006b77a5645f919aea76dd4926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> |
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| .. | ||
| cpu_ids.h | ||
| em64t100_save_state.h | ||
| em64t101_save_state.h | ||
| fsb.h | ||
| l2_cache.h | ||
| microcode.h | ||
| msr.h | ||
| post_codes.h | ||
| smm_reloc.h | ||
| speedstep.h | ||
| turbo.h | ||