coreboot/src
Duncan Laurie 0d0b3c5467 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS
The Chrome OS environment sends an SMI to finalize the chipset/board
at the end of the "depthcharge" payload, but there is no facility to
send this command if not using the full ChromeOS firmware stack.

This commit adds a callback before booting the payload that will
issue this SMI which will lock down the chipset and route USB devices
to the XHCI controller.

Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5181
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-18 18:22:51 +01:00
..
arch coreboot: infrastructure for different ramstage loaders 2014-02-15 18:39:29 +01:00
console console/uart8250*: Remove inclusion of mc146818rtc.h 2014-02-15 22:56:18 +01:00
cpu haswell: backup the default SMM region on resume 2014-02-16 20:42:41 +01:00
device PCI: Add capability list parser to romstage 2014-02-12 22:01:00 +01:00
drivers console: Add drivers/uart 2014-02-17 20:45:27 +01:00
ec chromeec: allow override of i8042 interrupt 2014-01-30 05:36:33 +01:00
include x86: provide infrastructure to backup default SMM region 2014-02-16 20:42:07 +01:00
lib x86: provide infrastructure to backup default SMM region 2014-02-16 20:42:07 +01:00
mainboard rambi: Set VBOOT_RAMSTAGE_INDEX to point to ramstage image 2014-02-17 18:55:59 +01:00
northbridge sandy/ivy: Fix mrc.cache file in CBFS 2014-02-17 06:13:31 +01:00
soc baytrail: add support to run reference code blob 2014-02-17 18:55:29 +01:00
southbridge lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS 2014-02-18 18:22:51 +01:00
superio superio/fintek: Document Fintek F71869AD code. 2014-02-13 17:14:20 +01:00
vendorcode coreboot: infrastructure for different ramstage loaders 2014-02-15 18:39:29 +01:00
Kconfig console: Add drivers/uart 2014-02-17 20:45:27 +01:00