Angel Pons 0c7a25069e soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR ... Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only. Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-10-12 17:37:26 +00:00
..
amd	soc/amd/cezanne/include/southbridge: add some more PM register defines	2021-10-11 15:15:41 +00:00
cavium	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSR	2021-10-12 17:37:26 +00:00
mediatek	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
nvidia	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
qualcomm	sc7280: Add SHRM firmware support	2021-10-07 09:03:05 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
sifive	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
ti
ucb