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coreboot/src/soc/intel
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Patrick Rudolph bc9757ff17 soc/intel/apollolake: Rename UART irqs 
Use the same names as on other intel socs.
Will be used in intel common uart driver.

Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10 10:45:46 +00:00
..
apollolake soc/intel/apollolake: Rename UART irqs 2020-08-10 10:45:46 +00:00
baytrail {sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code 2020-08-05 15:46:17 +00:00
braswell {sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code 2020-08-05 15:46:17 +00:00
broadwell soc/intel/broadwell/iobp: Log success in pch_iobp_write() 2020-08-07 11:57:32 +00:00
cannonlake soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devices 2020-08-10 10:44:59 +00:00
common soc/intel/common: Log CSE FW Status Registers before triggering recovery 2020-08-07 08:30:35 +00:00
denverton_ns cpu,soc/intel: Drop select SMP 2020-07-26 20:59:52 +00:00
icelake soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming 2020-08-09 11:03:37 +00:00
jasperlake soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming 2020-08-09 11:03:37 +00:00
quark src: Make HAVE_CF9_RESET set the FADT reset register 2020-07-20 13:23:13 +00:00
skylake soc/intel/skylake: Enable CIO depending on devicetree configuration 2020-08-08 16:32:41 +00:00
tigerlake soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming 2020-08-09 11:03:37 +00:00
xeon_sp vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc 2020-08-08 20:13:37 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00