Tim Wawrzynczak 0c0bcd4072 PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device ... This PCI ID is required in order for JSL devices to perform SSDT generation for DPTF. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-15 08:34:29 +00:00
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acpi	src/acpi/soundwire.c: Add missing <stddef.h>	2020-07-14 16:10:43 +00:00
arch	arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>'	2020-07-14 16:15:28 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	console: Update for vboot before bootblock	2020-06-15 22:07:12 +00:00
cpu	cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include	2020-07-14 16:15:09 +00:00
device	device/xhci: Add helper method to iterate over xhci_supported_protocl	2020-07-12 17:01:24 +00:00
drivers	src: Drop unused <cpu/x86/tsc.h> include	2020-07-14 16:14:33 +00:00
ec	ec/google: Add function ec_fill_dptf_helpers()	2020-07-07 20:31:30 +00:00
include	PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device	2020-07-15 08:34:29 +00:00
lib	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
mainboard	mainboard: Drop optional and empty ACPI \_BFS methods	2020-07-15 08:33:43 +00:00
northbridge	src: Remove unused 'include <cpu/x86/msr.h>'	2020-07-14 16:14:09 +00:00
security	src: Remove unused 'include <cpu/x86/msr.h>'	2020-07-14 16:14:09 +00:00
soc	PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device	2020-07-15 08:34:29 +00:00
southbridge	sb/intel/lynxpoint: Move acpi_fill_fadt to fadt.c	2020-07-14 22:33:06 +00:00
superio	superio/nuvoton: Avoid NULL pointer dereference	2020-07-12 19:40:53 +00:00
vendorcode	amd/picasso: rework DXIO and DDI UPD handling	2020-07-15 08:32:47 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00