Angel Pons 0a7d99c089 nb/intel/sandybridge: Fix handling of clock timing ... Clock is a differential signal and propagates faster than command and control, therefore its timing needs to be offset with `pi_code_offset`. It is also a periodic signal, so it can safely wrap around. To avoid potential undefined behavior, make `clk_delay` signed. It makes no difference with valid values, because the initial value can be proven to never be negative and `pi_code_offset` is always positive. With this change, it is possible to add an underflow check, for additional sanity. Change-Id: I375adf84142079f341b060fba5e79ce4dcb002be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2021-01-15 11:24:32 +00:00
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amd	kconfig: remove non-existent source	2020-12-28 13:37:56 +00:00
intel	nb/intel/sandybridge: Fix handling of clock timing	2021-01-15 11:24:32 +00:00