coreboot/src
Jimmy Zhang 099efebb1e ryu: Add and select DO_DSI_INIT config option
Enable display supporting functions by select DO_DSI_INIT

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush

Change-Id: Ie0e03506702ddab03d7f3fd2528c67c02126c7be
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 7133dfcd1a
Original-Change-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234272
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13 17:04:38 +02:00
..
arch urara: add support for DMA coherent memory area 2015-04-13 12:19:38 +02:00
console New mechanism to define SRAM/memory map with automatic bounds checking 2015-04-06 22:05:01 +02:00
cpu vendorcode/amd/agesa/f16kb: Enable support for AM1 socket 2015-04-10 15:29:24 +02:00
device cbfs: correct types used for accessing files 2015-04-01 22:51:10 +02:00
drivers spi: support controllers with limited transfer size capabilities 2015-04-13 13:01:33 +02:00
ec samus: Log EC panics to eventlog 2015-04-10 20:32:26 +02:00
include spi: support controllers with limited transfer size capabilities 2015-04-13 13:01:33 +02:00
lib vboot: Include vb2_api.h, instead of lower-level vboot2 header files 2015-04-10 16:49:15 +02:00
mainboard ryu: Add and select DO_DSI_INIT config option 2015-04-13 17:04:38 +02:00
northbridge northbridge/amd/agesa/familyXY: Make NULL device op explicit 2015-04-09 19:34:22 +02:00
soc ryu: Add and select DO_DSI_INIT config option 2015-04-13 17:04:38 +02:00
southbridge southbridge/intel/fsp_rangeley/ : Spellcheck + Formatting 2015-04-10 17:57:11 +02:00
superio kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
vendorcode Fix dependency issue in Chrome OS vendor code 2015-04-13 13:02:52 +02:00
Kconfig cbtables: Add RAM config information 2015-04-10 16:47:44 +02:00