Yu-Ping Wu 08d2016e50 soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz ... The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's HW design, which is capable of up to 52MHz. Therefore, lower the speed to univpll_d3_d8 (52MHz). BUG=b:218775654 TEST=emerge-corsola coreboot TEST=Boot time didn't increase significantly BRAHCH=none Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>		2022-02-11 14:07:18 +00:00
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common	soc/mediatek: Only update required bits when triggering WDT reset	2022-02-11 12:19:54 +00:00
mt8173	soc/mediatek/mt8173/dramc_pi_calibration_api.c: Remove duplicated "ERROR" in log message	2022-02-10 12:49:38 +00:00
mt8183	soc/mediatek: move i2c function to common folder	2021-11-17 10:29:55 +00:00
mt8186	soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz	2022-02-11 14:07:18 +00:00
mt8192	soc/mediatek: Extract dramc_param_header to a common header	2022-01-24 01:54:28 +00:00
mt8195	soc/mediatek/mt8186: Fix issue of clearing watchdog status	2022-02-09 06:04:18 +00:00
Kconfig