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coreboot/src/cpu/intel
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Kyösti Mälkki 08bf481667 UPSTREAM: intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE 
Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.

Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15761
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363384
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-07-26 12:27:09 -07:00
..
car UPSTREAM: intel car: Unify postcodes 2016-07-23 13:04:57 -07:00
common/acpi CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
ep80579 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
fit CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
fsp_model_206ax x86 chipsets: utilize x86_setup_mtrrs_with_detect() 2016-03-08 23:58:01 +01:00
fsp_model_406dx Remove #ifdef checks on Kconfig symbols 2015-12-06 18:46:12 +01:00
haswell UPSTREAM: intel/haswell: Remove useless MTRR clear 2016-07-24 10:19:30 -07:00
hyperthreading CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
microcode cpu/intel/microcode: allow microcode to be loaded in romstage 2016-02-10 18:08:28 +01:00
model_6bx tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_6dx CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_6ex UPSTREAM: intel car: Unify postcodes 2016-07-23 13:04:57 -07:00
model_6fx tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_6xx CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_65x tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_67x tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_68x tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_69x cpu: microcode: Use microcode stored in binary format 2015-09-30 06:57:19 +00:00
model_106cx UPSTREAM: intel model_106cx: Include CAR from socket directory 2016-07-23 13:04:50 -07:00
model_206ax UPSTREAM: intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE 2016-07-26 12:27:09 -07:00
model_1067x tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
model_2065x UPSTREAM: intel car: Unify postcodes 2016-07-23 13:04:57 -07:00
model_f0x CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_f1x CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_f2x CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_f3x CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
model_f4x CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
slot_1 UPSTREAM: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:45 -07:00
slot_2 CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
smm/gen1 CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
socket_441 UPSTREAM: intel model_106cx: Include CAR from socket directory 2016-07-23 13:04:50 -07:00
socket_BGA956 UPSTREAM: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:55 -07:00
socket_BGA1284 cpu/intel: Add socket BGA1284 2015-11-10 00:19:01 +01:00
socket_FC_PGA370 UPSTREAM: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:45 -07:00
socket_FCBGA559 UPSTREAM: intel model_106cx: Include CAR from socket directory 2016-07-23 13:04:50 -07:00
socket_LGA771 UPSTREAM: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:55 -07:00
socket_LGA775 UPSTREAM: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:55 -07:00
socket_LGA1155 cpu: get rid of socket source code 2015-05-04 22:18:23 +02:00
socket_mFCBGA479 UPSTREAM: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:45 -07:00
socket_mFCPGA478 UPSTREAM: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:55 -07:00
socket_mPGA478 cpu: get rid of socket source code 2015-05-04 22:18:23 +02:00
socket_mPGA479M UPSTREAM: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:45 -07:00
socket_mPGA603 cpu: get rid of socket source code 2015-05-04 22:18:23 +02:00
socket_mPGA604 UPSTREAM: intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:47 -07:00
socket_PGA370 UPSTREAM: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP 2016-06-22 10:40:45 -07:00
socket_rPGA988B Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
socket_rPGA989 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
speedstep tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
thermal_monitoring CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
turbo tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
Kconfig cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx 2015-11-24 14:39:42 +01:00
Makefile.inc Make MRC vs native a config rather than making a separate chipset for it. 2016-02-12 17:09:05 +01:00