Nico Huber 08bee23f7e intel/gm45: Refactor DDR3 write training ... Split some code in individual functions. It's the refactoring part of a bigger change, following... Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3255 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2013-05-22 18:04:11 +02:00
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arch	Drop llshell	2013-05-20 08:42:28 +02:00
console	Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary	2013-05-10 17:33:49 +02:00
cpu	haswell: enable cache-as-ram migration	2013-05-16 01:30:25 +02:00
device	Get rid of a number of __GNUC__ checks	2013-05-10 17:31:31 +02:00
drivers	pc80/tpm: allow for cache-as-ram migration	2013-05-16 01:29:59 +02:00
ec	ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT	2013-04-18 02:47:23 +02:00
include	x86: add cache-as-ram migration option	2013-05-16 01:29:50 +02:00
lib	cbmem console: use cache-as-ram API and cleanup	2013-05-16 01:30:17 +02:00
mainboard	ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case	2013-05-20 18:33:23 +02:00
northbridge	intel/gm45: Refactor DDR3 write training	2013-05-22 18:04:11 +02:00
southbridge	AMD AGESA Hudson: Include stdint.h and io.h to fix build	2013-05-20 18:34:18 +02:00
superio	Drop prototype guarding for romcc	2013-05-10 00:06:46 +02:00
vendorcode	chromeos: use cache-as-ram migration API for vbnv	2013-05-16 01:30:09 +02:00
Kconfig	Drop llshell	2013-05-20 08:42:28 +02:00