Musse Abdullahi 08545aa302 soc/intel/meteorlake: Add QS(C0) stepping CPU ID ... This patch adds CPU ID for C0 stepping (aka QS). DOC=#723567 TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log. Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2023-06-29 17:08:17 +00:00
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amd	soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error	2023-06-28 13:57:31 +00:00
cavium	soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register	2023-05-13 17:22:16 +00:00
example/min86
intel	soc/intel/meteorlake: Add QS(C0) stepping CPU ID	2023-06-29 17:08:17 +00:00
mediatek	soc/mediatek: Enable DRAM scramble on fast calibration flow	2023-06-26 02:23:21 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	treewide: Remove 'extern' from functions declaration	2023-05-26 13:45:24 +00:00
rockchip
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	soc/sifive: Comment out set but unused variables	2023-06-04 19:22:50 +00:00
ti
ucb/riscv