coreboot/src
Aaron Durbin 083b21b354 rush: use padconfig API in bootblock
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.

BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on rush. Observed consistent results.

Change-Id: Ibfa6fc188a7c503cfad41420ed50c7a88fdec579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2245478f8e
Original-Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210836
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24 15:28:19 +01:00
..
arch vboot2: separate verstage from bootblock 2015-03-24 14:48:04 +01:00
console console: Allow bootblock console on MIPS 2015-03-23 15:35:06 +01:00
cpu imgtec/danube: Add support for ImgTec Danube SoC 2015-03-21 16:57:08 +01:00
device PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
drivers vboot2: read secdata and nvdata 2015-03-23 19:51:47 +01:00
ec chromeec: use stopwatch API 2015-03-21 17:00:26 +01:00
include vboot2: factory-initialize kernel space in tpm 2015-03-24 15:19:54 +01:00
lib vboot2: load decompressed stage directly to load address 2015-03-24 15:19:21 +01:00
mainboard rush: use padconfig API in bootblock 2015-03-24 15:28:19 +01:00
northbridge cpu/amd/model_10xxx: Add support for early cbmem 2015-03-19 08:28:43 +01:00
soc tegra132: add bootblock_mainboard_early_init() 2015-03-24 15:28:16 +01:00
southbridge CBMEM: Add LATE_CBMEM_INIT guards 2015-03-19 06:17:07 +01:00
superio superio: ite8772f: Exit extemp busy state 2015-03-21 08:44:28 +01:00
vendorcode rk3288: update romstage & mainboard 2015-03-24 15:25:31 +01:00
Kconfig Enable publishing of board ID where supported 2015-03-23 17:20:24 +01:00