Ronak Kanabar c72df501a1 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01 ... The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-07-30 17:32:49 +00:00
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amd	soc/amd/cezanne: enable crypto in psp_verstage	2021-07-21 16:53:17 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE	2021-07-28 08:19:30 +00:00
google	timestamp,vc/google/chromeos/cr50: Add timestamp for enable update	2021-07-05 10:50:06 +00:00
intel	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01	2021-07-30 17:32:49 +00:00
mediatek	vc/mediatek/mt8195: Improve DRAM stability by impedance tracking	2021-07-28 02:51:36 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00