coreboot/src/include/gic.h
Elyes HAOUAS 5912b4408d UPSTREAM: src/include: Capitalize CPU, RAM and ROM
BUG=None
BRANCH=None
TEST=None

Change-Id: Ifd528bc4ac07658453407c0392d6653325217bbb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15942
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/366263
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-08-04 23:37:08 -07:00

39 lines
1.1 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef GIC_H
#define GIC_H
#if IS_ENABLED(CONFIG_GIC)
/* Initialize the GIC on the currently processor, including GICD and GICC. */
void gic_init(void);
void gic_disable(void);
void gic_enable(void);
/* Return a pointer to the base of the GIC distributor mmio region. */
void *gicd_base(void);
/* Return a pointer to the base of the GIC CPU mmio region. */
void *gicc_base(void);
#else /* CONFIG_GIC */
static inline void gic_init(void) {}
static inline void gic_disable(void) {}
#endif /* CONFIG_GIC */
#endif /* GIC_H */