coreboot/src/northbridge/intel
Patrick Rudolph 55409ebbb6 nb/intel/sandybridge/raminit: Use supported CAS
Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.

Useful for overclocking.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.

Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15217
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20 22:00:40 +02:00
..
common nb/intel: Factor out common MRC code 2016-06-12 12:27:32 +02:00
e7501 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
e7505 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
fsp_rangeley header files: Fix guard name comments to match guard names 2016-01-18 04:07:53 +01:00
fsp_sandybridge northbridge/intel: move mrc_cache definition into a common header 2016-03-11 18:56:21 +01:00
gm45 nb/intel/raminit (native): Read PCI mmio size from devicetree 2016-06-12 12:48:44 +02:00
haswell nb/intel: Factor out common MRC code 2016-06-12 12:27:32 +02:00
i440bx northbridge/intel/i440bx: Unify UDELAY selection 2016-03-10 16:55:35 +01:00
i855 northbridge/intel: add missing #include guards 2016-02-28 18:55:32 +01:00
i945 Move definitions of HIGH_MEMORY_SAVE 2016-06-17 00:19:08 +02:00
i3100 cpu/x86/mtrr: move cache_ramstage() to its only user 2016-03-16 18:55:51 +01:00
i5000 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
i82810 northbridge/intel/i82810: Unify UDELAY selection 2016-03-13 00:46:55 +01:00
i82830 northbridge/intel/i82830: Unify UDELAY selection 2016-03-12 22:03:42 +01:00
nehalem nb/intel/raminit (native): Read PCI mmio size from devicetree 2016-06-12 12:48:44 +02:00
pineview intel/pineview: Don't try to store 34 bits in 32 2016-05-08 21:36:32 +02:00
sandybridge nb/intel/sandybridge/raminit: Use supported CAS 2016-06-20 22:00:40 +02:00
x4x nb/intel/x4x: Fix unpopulated value 2016-06-04 23:46:05 +02:00