Arthur Heymans 06f818c932 cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x ... According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" the SMRR MSR are at a different offset for model_6fx and model_1067x. This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL. Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2018-07-30 19:03:27 +00:00
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amd	src/{ec,include,lib}: Use "foo *bar" instead of "foo* bar"	2018-07-09 09:28:35 +00:00
intel	cpu/intel/microcode: Add helper functions to get microcode info	2018-07-30 18:49:47 +00:00
x86	cpu/intel/smm/gen1: Use correct MSR for model_6fx and model_1067x	2018-07-30 19:03:27 +00:00
cpu.h	Rename __attribute__((packed)) --> __packed	2017-07-13 19:45:59 +00:00