Marc Jones 067d22340c Fix ECC disable option for AMD Fam10 DDR2 and DDR3. ... The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/670 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2012-03-02 23:35:26 +01:00
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arch/x86	Fix x86 cpu_phys_address_size	2012-02-29 20:58:14 +01:00
boot	selfboot: Don't include unneeded ip_checksum.h	2011-11-08 21:21:55 +01:00
console	trivial:change the value type of POST_PORT in Kconfig from int to hex	2011-12-26 08:52:07 +01:00
cpu	Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.	2012-02-20 05:37:26 +01:00
devices	Revert "Fix multipleVGA cards resource conflict on Windows"	2012-02-23 01:29:36 +01:00
drivers	Ati video: Apply un-written naming rules	2012-02-24 11:21:48 +01:00
ec	X60/T60: Add option to enable/disable bluetooth	2012-01-31 18:03:40 +01:00
include	pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids	2012-02-16 19:27:29 +01:00
lib	Remove whitespace.	2012-02-17 19:04:31 +01:00
mainboard	Rename vendor identifiers in Kconfig	2012-03-01 00:03:15 +01:00
northbridge	Fix ECC disable option for AMD Fam10 DDR2 and DDR3.	2012-03-02 23:35:26 +01:00
pc80	vga: removed inclusion of .c files	2012-01-27 20:07:00 +01:00
southbridge	AMD southbridge: remove sp5100	2012-02-29 01:42:31 +01:00
superio	SIO: Add smsc sio1036 superio	2012-02-17 17:19:34 +01:00
vendorcode	SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code	2012-02-02 15:05:36 +01:00
Kconfig	Move SeaBIOS output out of coreboot source tree	2012-02-07 00:21:03 +01:00
Kconfig.deprecated_options	Unify ID_SECTION_OFFSET and mark it deprecated	2012-01-18 11:21:39 +01:00