Marshall Dawson 06766c1efa amd/stoneyridge: Remove PSP BAR init from cpu init ... Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-09-13 18:57:42 +00:00
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amd	amd/stoneyridge: Remove PSP BAR init from cpu init	2017-09-13 18:57:42 +00:00
broadcom/cygnus	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
dmp/vortex86ex	soc/dmp/vortex86: Fix CMOS read and random RTC reset	2017-08-01 13:20:15 +00:00
imgtec/pistachio	Consolidate reset API, add generic reset_prepare mechanism	2017-06-13 20:53:09 +02:00
intel	soc/intel/cannonlake: Add ramstage uart debug support	2017-09-13 17:25:02 +00:00
lowrisc/lowrisc	soc/lowrisc: Place CBMEM at top of autodetected RAM	2016-12-06 18:51:13 +01:00
marvell/mvmap2315	Update files with no newline at the end	2017-07-24 15:08:16 +00:00
mediatek/mt8173	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
nvidia	nvidia/tegra*: Use xcompile for compiler prefix unless specified	2017-09-05 20:17:30 +00:00
qualcomm	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
rockchip	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
samsung	include/device: Split i2c.h into three	2017-08-18 15:33:29 +00:00
ucb/riscv	soc/ucb/riscv: Place CBMEM at top of autodetected RAM	2016-12-06 18:48:28 +01:00