The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
BUG=none
BRANCH=none
TEST=none
Change-Id: I9ebdb696f63706590bf864f4b3e11304a1f7a1b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: bb5fb64e11
Original-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19556
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/531202
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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