coreboot/src/soc
Patrick Rudolph 05bad430b6 soc/intel/common/block/sgx: Fix crash in MP init
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.

To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.

Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.

Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.

Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15 08:19:02 +00:00
..
amd device: Use scan_static_bus() over scan_lpc_bus() 2019-10-08 12:59:56 +00:00
cavium devicetree: Fix improper use of chip_operations 2019-10-04 16:29:31 +00:00
imgtec cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
intel soc/intel/common/block/sgx: Fix crash in MP init 2019-10-15 08:19:02 +00:00
mediatek soc/mediatek/mt8183: Change argument type of mt_set_emi 2019-10-09 22:24:00 +00:00
nvidia cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
qualcomm soc/qualcomm: Remove default ops to generate bootblock.bin 2019-10-09 22:24:56 +00:00
rockchip arm64: Uprev Arm TF and adjust to BL31 parameter changes 2019-09-14 05:01:16 +00:00
samsung cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
sifive soc/sifive/fu540: add code for spi and map flash to memory spaces 2019-08-12 08:35:17 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00