coreboot/src/mainboard/pcengines
Krystian Hebel fba0320842 mb/pcengines/apu2/romstage.c: disable SVI2 wait completion
On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.

Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-28 22:39:40 +00:00
..
apu1 mainboard: Remove useless include <device/pci_ids.h> 2018-12-19 05:23:18 +00:00
apu2 mb/pcengines/apu2/romstage.c: disable SVI2 wait completion 2018-12-28 22:39:40 +00:00
Kconfig kconfig: automatically include mainboards 2015-04-18 08:31:08 +02:00
Kconfig.name kconfig: automatically include mainboards 2015-04-18 08:31:08 +02:00