coreboot/src
Aaron Durbin 0531fda146 haswell: calibrate 24MHz clock against BCLK
On haswell ULT systems there is a 24MHz clock that continuously runs
when deep package c-states are entered. The 100MHz BCLK is shut down
in the lower c-states. When the package wakes back up a conversion
formula needs to be applied. The 24MHz calibration is done using the
internal PCODE unit.

BUG=None
BRANCH=None
TEST=Booted but as we have package c-states disabled this change doesn't
     have much of an impact at the moment.

Change-Id: I6be7702fb1de1429273724536f5af9125b98da64
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48292
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
2013-04-23 16:50:45 -07:00
..
arch armv7: specify condition code for msr instruction 2013-04-08 18:31:08 +02:00
console console: Make use of CONFIG_USE_OPTION_TABLE 2013-04-01 20:54:48 +02:00
cpu haswell: calibrate 24MHz clock against BCLK 2013-04-23 16:50:45 -07:00
device Add PXE ROM selection to Kconfig menu 2013-04-03 18:01:44 +02:00
drivers x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
ec ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT 2013-04-09 13:45:43 -07:00
include Eliminate use of pointers in coreboot table 2013-04-22 11:57:06 -07:00
lib Eliminate use of pointers in coreboot table 2013-04-22 11:57:06 -07:00
mainboard fox_wtm2: First step support for coreboot-based graphics startup 2013-04-23 15:50:48 -07:00
northbridge fox_wtm2: First step support for coreboot-based graphics startup 2013-04-23 15:50:48 -07:00
southbridge lynxpoint: Build intermediate step to add LynxPoint ME image 2013-04-19 11:46:15 -07:00
superio Winbond W83627HF: Rename and move ASL snippet to acpi/superio.asl 2013-04-01 21:09:24 +02:00
vendorcode Eliminate use of pointers in coreboot table 2013-04-22 11:57:06 -07:00
Kconfig dynamic cbmem: fix memconsole and timestamps 2013-03-23 19:44:25 +01:00