coreboot/src
Patrick Rudolph 052163236c mb/lenovo: Add SMBIOS type 9 for ExpressCard
Mark all known PCIe root ports as ExpressCard slot.

Tested on Lenovo T520.

Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-07 16:06:55 +00:00
..
acpi
arch smbios: Walk over PCI devicetree to fill type 9 2019-05-07 16:05:53 +00:00
commonlib src: include <assert.h> when appropriate 2019-04-23 10:01:36 +00:00
console Fix code that would trip -Wtype-limits 2019-05-06 10:32:15 +00:00
cpu cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZE 2019-04-25 15:56:28 +00:00
device device: ignore NONE devices behind bridge 2019-05-07 16:05:27 +00:00
drivers intel/fsp1_1: Drop remnants of pei_data 2019-05-07 15:59:10 +00:00
ec ec/google/wilco: Support board_id with EC provided ID 2019-04-18 23:43:06 +00:00
include sconfig: Add SMBIOS type 9 entries 2019-05-07 16:04:56 +00:00
lib vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
mainboard mb/lenovo: Add SMBIOS type 9 for ExpressCard 2019-05-07 16:06:55 +00:00
northbridge {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function 2019-05-07 15:52:01 +00:00
security vboot: remove use of GoogleBinaryBlockHeader 2019-05-06 12:40:31 +00:00
soc mb/google/sarien: Add SMBIOS type 9 fields 2019-05-07 16:06:39 +00:00
southbridge sb/intel/bd82x6x: Fix flashconsole after lockdown 2019-05-07 16:04:07 +00:00
superio superio/fintek/f71808a: Add more optional ramstage registers 2019-05-01 00:09:57 +00:00
vendorcode Fix code that would trip -Wtype-limits 2019-05-06 10:32:15 +00:00
Kconfig spd_bin: Do not depend CONFIG_DIMM_MAX on CONFIG_GENERIC_SPD_BIN 2019-05-06 10:31:38 +00:00