coreboot/src/northbridge/intel
Elyes Haouas 0509009f79 nb/intel/gm45/raminit: Use read32p()
Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom
remains identical.

Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-08 13:03:45 +00:00
..
common nb/intel/common: Replace _bar_clrsetbits_impl macro 2021-05-03 07:38:52 +00:00
e7505 device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
gm45 nb/intel/gm45/raminit: Use read32p() 2024-01-08 13:03:45 +00:00
haswell device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
i440bx device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
i945 device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
ironlake Use common GCD function 2023-11-04 17:06:42 +00:00
pineview device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00
sandybridge northbridge/intel/sandybridge: Enable x86_64 for mrc.bin 2024-01-05 14:34:29 +00:00
x4x device/device.h: Rename pci_domain_scan_bus 2023-10-20 14:24:57 +00:00