Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. ... Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>		2011-08-04 08:10:12 +02:00
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acpi.h	For completeness sake: License header.	2010-11-18 00:46:53 +00:00
hyperthreading.h	- Renamed cpu header files	2004-10-14 20:13:01 +00:00
l2_cache.h	cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.	2011-08-04 08:10:12 +02:00
microcode.h	fix compiler warnings (trivial)	2009-01-20 21:27:23 +00:00
speedstep.h	factor out cpu power management base into a separate file. And fix a bug in	2010-12-11 22:14:44 +00:00