coreboot/src/soc
Vadim Bendebury 04884b65cc rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHz
Previous code had several problems:
* It was only initting 3 of the 4 voltage rails hooked up to PWM
  regulators.
* It was using a PWM frequency that was out of range.  Apparently from
  testing 300kHz is best.
* It was initting all rails to .9V.  On my Kevin I needed 1.1V to make
  booting all 6 cores / rebooting reliable.

With this fix both booting all 6 cores in the kernel is reliable (if we
tell the kernel not to touch the PWM) and the "reboot" command from
Linux userspace is also reliable (previously it crashed in coreboot).

NOTES:
* Setting all rails to the same voltage doesn't make a lot of sense.  We
  should figure out what these should _actually_ be.  Presumably the
  little CPU rail can be lower, at least.  ...and we don't use the GPU
  in the BIOS so we should set that lower.

BRANCH=none
BUG=chrome-os-partner:51922
TEST=reboot test

Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e
Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/339151
Reviewed-on: https://review.coreboot.org/14727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:49:24 +02:00
..
broadcom/cygnus soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
dmp/vortex86ex dmp/vortex86ex: Merge northbridge and southbridge into soc 2016-05-05 20:06:33 +02:00
imgtec/pistachio imgtec/pistachio: Fix memlayout ASSERT with new binutils 2016-04-21 07:16:06 +02:00
intel soc/intel/skylake: Enable another VR mailbox command for certain boards 2016-05-09 08:28:57 +02:00
marvell src/soc/marvell: Update license headers 2016-04-13 17:34:33 +02:00
mediatek/mt8173 soc/mediatek/mt8173: mt6391: vcore sleep voltage should be 0.7V 2016-05-09 08:36:57 +02:00
nvidia tegra124: Align the framebuffer's bytes-per-line to 32 2016-05-09 07:49:05 +02:00
qualcomm/ipq806x ipq806x/storm: Return NULL for cbmem_top if DRAM is not initialized 2016-03-29 22:37:01 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHz 2016-05-09 08:49:24 +02:00
samsung soc/*: fix uart's regwidth specification in cbtables 2016-02-21 12:26:05 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00