coreboot/src
Martin Roth 037ee4b556 soc/amd/picasso: Add dummy spinlock for psp_verstage
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing.  Add dummy spinlock code as the spinlocks
aren't needed in the PSP.

TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09 00:26:05 +00:00
..
acpi acpigen: Add acpigen_notify 2020-07-07 20:31:22 +00:00
arch arch/x86: Add memmove.c to x86 bootblock 2020-07-08 21:06:47 +00:00
commonlib lib/coreboot_table: Add Intel FSP version to coreboot table 2020-07-04 11:20:08 +00:00
console console: Update for vboot before bootblock 2020-06-15 22:07:12 +00:00
cpu haswell: relocate romstage_common to northbridge 2020-07-08 22:16:58 +00:00
device Kconfig: Escape variable to accommodate new Kconfig versions 2020-06-19 15:29:04 +00:00
drivers dptf: Add support for IDSP 2020-07-07 17:23:47 +00:00
ec ec/google: Add function ec_fill_dptf_helpers() 2020-07-07 20:31:30 +00:00
include ACPI: Add and fill gnvs_ptr for smm_runtime 2020-07-08 07:32:51 +00:00
lib lib: Temporarily remove timestamps from psp_verstage 2020-07-08 19:37:50 +00:00
mainboard mb/google/zork: Do not select VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for Vilboz 2020-07-08 23:07:50 +00:00
northbridge haswell: relocate romstage_common to northbridge 2020-07-08 22:16:58 +00:00
security security/vboot: Allow files to go into only RW-A or RW-B region 2020-07-08 19:36:24 +00:00
soc soc/amd/picasso: Add dummy spinlock for psp_verstage 2020-07-09 00:26:05 +00:00
southbridge sb/intel/lynxpoint: Program PM registers directly 2020-07-08 22:26:15 +00:00
superio superio/winbond/w83977tf: Add suspend related fields 2020-06-16 20:17:26 +00:00
vendorcode vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc 2020-07-07 22:24:41 +00:00
Kconfig arch/x86: Remove RELOCATABLE_RAMSTAGE 2020-07-06 06:17:47 +00:00