coreboot/mainboard
Ronald G. Minnich 010f751a48 With this set of changes FILO now reliably finds the IDE controller.
Press <Enter> for default boot, or <Esc> for boot prompt...  
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4

Sadly, it locks up at this point, but this is still progress.

I realize the location of the defines is a little odd, but I think it is useful to have 
them right next to the function that uses them. 

Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts. 
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-07 06:33:49 +00:00
..
adl Cache the ROM to speed up stage2 and payload decompression. 2008-02-06 02:36:50 +00:00
amd Cache the ROM to speed up stage2 and payload decompression. 2008-02-06 02:36:50 +00:00
artecgroup Cache the ROM to speed up stage2 and payload decompression. 2008-02-06 02:36:50 +00:00
emulation Fix compilation for qemu/x86 by renaming pre_payload() to 2008-02-06 03:12:53 +00:00
pcengines With this set of changes FILO now reliably finds the IDE controller. 2008-02-07 06:33:49 +00:00
Kconfig Now version 3: LinuxBIOS -> coreboot rename. 2008-01-27 18:54:57 +00:00