Lijian Zhao 55cad16ca5 mainboard/google/reef: Config needed GPIO for pull-up WA ... This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2017-05-12 20:19:40 +02:00
..
variants	mainboard/google/reef: Config needed GPIO for pull-up WA	2017-05-12 20:19:40 +02:00
acpi_tables.c
board_info.txt
boardid.c	mainboard/google/reef: add variant API for board_id and gpio	2016-09-06 20:04:18 +02:00
bootblock.c	mainboards,ec: provide common declaration for mainboard_ec_init()	2016-09-26 23:53:12 +02:00
chromeos.c	vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default	2017-03-28 22:15:46 +02:00
chromeos.fmd	mainboard/google/reef: Add FPF_STATUS FMAP region	2017-03-15 03:42:55 +01:00
dsdt.asl	mainboards/google/reef: use chromeec's ASL lid switch implementation	2016-09-26 23:52:53 +02:00
ec.c	mainboards,ec: provide common declaration for mainboard_ec_init()	2016-09-26 23:53:12 +02:00
Kconfig	mb/google/reef: enable SAR and DSAR	2017-05-08 06:10:12 +02:00
Kconfig.name	mainboard/google/reef: add nasher variant	2017-03-22 03:43:38 +01:00
mainboard.c	mainboard/google/reef: fill in NHLT ACPI OEM header fields	2016-12-09 17:26:54 +01:00
Makefile.inc	google/reef: Remove VARIANT_DIR definition	2016-12-15 17:39:12 +01:00
romstage.c	mainboard/google/reef: add baseboard memory configuration	2016-09-06 20:16:32 +02:00
smihandler.c	google/reef: Remove setting of GPIO_TIER1_SCI enable bit	2016-09-15 01:20:06 +02:00