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Author SHA1 Message Date
Felix Singer
54d0cc9a3c util/crossgcc: Use GitHub for downloading IASL
The download links from acpica.org [1] are not stable, and for some
reason they named the release tarballs with .tar_0.gz. Thus, use the
tarballs from their GitHub repository generated out of the release
tags [2].

Tested locally and also IASL patch applies.

[1] https://www.acpica.org/downloads
[2] https://github.com/acpica/acpica/tags

Original-signed-off-by: Felix Singer <felixsinger@posteo.net>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/70021
Original-reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Original-reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Cherry-picked-from: 60a422736b
Change-Id: I7b10dd1db4299aaef96bc29023bed874b660aba0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-17 15:49:09 +00:00
Elyes Haouas
128c49e4e6 crossgcc: Upgrade IASL from 20220331 to 20221020
Changes: https://acpica.org/node/201

Original-signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/68929
Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-reviewed-by: Felix Singer <felixsinger@posteo.net>

Cherry-picked-from: a45ed44724
Change-Id: I386a6757a318336bc616091afe0c4ed88cd89583
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-17 15:48:53 +00:00
Arthur Heymans
5b38099abe Makefile.inc: Remove workaround ACPI warnings
No boards now have a missing dependency so remove the workaround.

Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/69514
Original-reviewed-by: Nico Huber <nico.h@gmx.de>
Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Original-reviewed-by: Felix Held <felix-coreboot@felixheld.de>

Cherry-picked-from: 457f77be37
Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-12 02:16:16 +00:00
Arthur Heymans
d5ef6be38e {ec/superio}/acpi: Remove _PRS if no _SRS is implemented
_PRS only makes sense if _SRS is implemented.

Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/69513
Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

Cherry-picked-from: 87d4f114a2
Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-12 02:15:34 +00:00
Arthur Heymans
52473bd79c superio/acpi/pnp_generic.asl: Add _PRS for each device
Simply return the current resource settings in the _PRS method. This
means that coreboot has to correctly set up the resources on the
device. This won't result in any regression as without _PRS the ACPI
OS would not know what resources settings are valid, so it would never
use _SRS.

Original-signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/64218
Original-reviewed-by: Nico Huber <nico.h@gmx.de>
Original-reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Original-tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

Cherry-picked-from: 148fd99365
Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70903
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-12 02:15:09 +00:00
Paul Menzel
75f1500cb6 Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
commit ac23f9da75 upstream.

GCC 12 incorrectly warns about an array out of bounds issue:

```
$ make V=1 # emulation/qemu-i440fx
[…]
    CC         ramstage/arch/x86/ebda.o
x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32  -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c
In file included from src/arch/x86/ebda.c:6:
In function 'write_ble8',
    inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2,
    inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2,
    inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2,
    inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2:
src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds]
   27 |         *(uint8_t *)dest = val;
      |         ~~~~~~~~~~~~~~~~~^~~~~
[…]
```

[In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1]
It treats INTEGER_CST addresses smaller than that as assumed results of
pointer arithmetics from NULL while addresses equal or larger than that
as expected user constant addresses. For GCC 13 we can represent results
from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead
of (void*)offset INTEGER_CSTs.

[1]: https://web.archive.org/web/20220711061810/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578

TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0
Original-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/62830
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Change-Id: I90dc714f1959e94e9dc53cd383db19dc0dd9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-09 04:01:35 +00:00
Matt DeVillier
dba310c554 soc/intel/apollolake: Skip SMI lockdown on Apollolake
Commit d9ef02ce (soc/intel/apollolake: Lock down Global SMI) breaks
SMM/SMI on Apollolake (but not Geminilake), so guard it accordingly.

TEST=build/boot google/reef, verify SMM/SMI/SMMSTORE functional.

Change-Id: I00cbe046b61e6c342f7961670478d0ca8d365c2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:31:35 +00:00
Matt DeVillier
c4c0f00a57 drivers/tpm: Move TPM init to end of device init phase
Boards which use an I2C TPM and do not use vboot will not have the
I2C bus initialized/ready at the start of the device init phase.
If TPM init is called before the bus, init will fail with I2C
transfer timeouts and a significantly lengthened boot time.

Resolves: https://ticket.coreboot.org/issues/429

TEST=build/boot google/reef w/o vboot, verify successful TPM init.

Change-Id: Ic47e465db1c06d8b79a1f0a06906843149b6dacd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-20 17:23:29 +00:00
28 changed files with 17 additions and 223 deletions

View file

@ -265,26 +265,9 @@ endef
# ResourceTemplate is the correct code.
# As it's valid ASL, disable the warning.
EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
# 1) If _PRS is present, must have _CRS and _SRS
# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
# 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
# 4) If _SRS is present, probably should have a _DIS (Remark only)
# A warning will be issued for each of these cases.
# For existing ASL code, ignore this warnings
IASL_MISSING_DEPENDENCY = 3141
IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING)
ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
build_complete::
printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n"
printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
endif
IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
define asl_template

View file

@ -10,4 +10,4 @@ static void init_tpm_dev(void *unused)
tpm_setup(s3resume);
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, init_tpm_dev, NULL);
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, init_tpm_dev, NULL);

View file

@ -29,25 +29,6 @@ Device (WLCO)
CONFIG_EC_BASE_PACKET,
16, 16)
})
Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
IO (Decode16,
CONFIG_EC_BASE_HOST_DATA,
CONFIG_EC_BASE_HOST_DATA,
4, 4)
IO (Decode16,
CONFIG_EC_BASE_HOST_COMMAND,
CONFIG_EC_BASE_HOST_COMMAND,
4, 4)
IO (Decode16,
CONFIG_EC_BASE_PACKET,
CONFIG_EC_BASE_PACKET,
16, 16)
}
EndDependentFn ()
})
}
Device (WEVT)

View file

@ -26,15 +26,6 @@ Device (SIO)
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
IRQNoFlags () {4}
})
Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08)
IRQNoFlags () {4}
}
EndDependentFn ()
})
}
Device (PS2K)
@ -58,16 +49,6 @@ Device (SIO)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQ (Edge, ActiveHigh, Exclusive) {1}
})
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0) {
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQ (Edge, ActiveHigh, Exclusive) {1}
}
EndDependentFn ()
})
}
Device (PS2M)
@ -88,13 +69,5 @@ Device (SIO)
{
IRQ (Edge, ActiveHigh, Exclusive) {12}
})
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0) {
IRQ (Edge, ActiveHigh, Exclusive) {12}
}
EndDependentFn ()
})
}
}

View file

@ -24,16 +24,6 @@ Device (SIO) {
FixedIO (0x64, 0x01)
IRQNoFlags () {1}
})
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0) {
FixedIO (0x60, 0x01)
FixedIO (0x64, 0x01)
IRQNoFlags () {1}
}
EndDependentFn ()
})
}
#endif
}

View file

@ -25,17 +25,6 @@ Device (SIO)
FixedIO (0x64, 0x01)
IRQNoFlags () {1}
})
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0)
{
FixedIO (0x60, 0x01)
FixedIO (0x64, 0x01)
IRQNoFlags () {1}
}
EndDependentFn ()
})
}
#endif
@ -55,17 +44,6 @@ Device (SIO)
FixedIO (0x64, 0x01)
IRQNoFlags () {12}
})
Name (_PRS, ResourceTemplate()
{
StartDependentFn (0, 0)
{
FixedIO (0x60, 0x01)
FixedIO (0x64, 0x01)
IRQNoFlags () {12}
}
EndDependentFn ()
})
}
#endif

View file

@ -2,9 +2,6 @@
if BOARD_ACER_G43T_AM3
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_LGA775

View file

@ -2,9 +2,6 @@
if BOARD_ASROCK_H81M_HDS
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_4096

View file

@ -14,9 +14,6 @@ config BOARD_ASUS_H61_SERIES
if BOARD_ASUS_H61_SERIES
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config MAINBOARD_DIR
default "asus/h61-series"

View file

@ -2,9 +2,6 @@
if BOARD_ASUS_P5QPL_AM || BOARD_ASUS_P5G41T_M_LX
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_LGA775

View file

@ -2,9 +2,6 @@
if BOARD_FOXCONN_D41S
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_FCBGA559

View file

@ -2,9 +2,6 @@
if BOARD_FOXCONN_G41S_K || BOARD_FOXCONN_G41M
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_LGA775

View file

@ -2,9 +2,6 @@
if BOARD_GIGABYTE_GA_D510UD
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_512

View file

@ -1,8 +1,5 @@
if BOARD_INTEL_DCP847SKE
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192

View file

@ -2,9 +2,6 @@
if BOARD_INTEL_DG41WV
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_LGA775

View file

@ -2,9 +2,6 @@
if BOARD_INTEL_DG43GT
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_INTEL_SOCKET_LGA775

View file

@ -1,8 +1,5 @@
if BOARD_INTEL_EMERALDLAKE2
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select NORTHBRIDGE_INTEL_SANDYBRIDGE

View file

@ -2,9 +2,6 @@
if BOARD_SUPERMICRO_X10SLM_PLUS_F
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384

View file

@ -1,8 +1,5 @@
if BOARD_SUPERMICRO_X9SCL
config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192

View file

@ -18,5 +18,6 @@ static void pmc_lock_smi(void)
void soc_lockdown_config(int chipset_lockdown)
{
/* APL only supports CHIPSET_LOCKDOWN_COREBOOT */
pmc_lock_smi();
if (CONFIG(SOC_INTEL_GEMINILAKE))
pmc_lock_smi();
}

View file

@ -171,4 +171,12 @@ Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
Store (One, PNP_DEVICE_ACTIVE)
EXIT_CONFIG_MODE ()
}
/* This is used for _SRS. Since _DIS only disables the device
* without changing the resources this works.
*/
Method (_PRS, 0)
{
return (_CRS)
}
}

View file

@ -108,12 +108,6 @@ Device (SIO) {
IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
})
OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
Field (ECAP, ByteAcc, NoLock, Preserve)
{
@ -151,12 +145,6 @@ Device (SIO) {
IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
})
}
#endif
@ -175,11 +163,6 @@ Device (SIO) {
IRQNoFlags () {4}
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
})
}
#endif
@ -200,12 +183,6 @@ Device (SIO) {
IRQNoFlags () {1}
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQNoFlags () {1}
})
}
#endif
@ -223,10 +200,6 @@ Device (SIO) {
IRQNoFlags () {12}
})
Name (_PRS, ResourceTemplate()
{
IRQNoFlags () {12}
})
}
#endif
@ -247,13 +220,6 @@ Device (SIO) {
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
IRQNoFlags () {6}
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
}
#endif
@ -272,11 +238,6 @@ Device (SIO) {
IRQNoFlags () { SIO_INFR_IRQ }
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
IRQNoFlags () { SIO_INFR_IRQ }
})
}
#endif
}

View file

@ -108,12 +108,6 @@ Device (SIO) {
IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
})
OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
Field (ECAP, ByteAcc, NoLock, Preserve)
{
@ -151,12 +145,6 @@ Device (SIO) {
IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
})
}
#endif
@ -174,12 +162,6 @@ Device (SIO) {
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
})
Name (_PRS, ResourceTemplate ()
{
IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
IRQNoFlags () {4}
})
}
#endif
@ -199,13 +181,6 @@ Device (SIO) {
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQNoFlags () {1}
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, 0x60, 0x60, 0x01, 0x01)
IO (Decode16, 0x64, 0x64, 0x01, 0x01)
IRQNoFlags () {1}
})
}
#endif
@ -222,11 +197,6 @@ Device (SIO) {
{
IRQNoFlags () {12}
})
Name (_PRS, ResourceTemplate()
{
IRQNoFlags () {12}
})
}
#endif
@ -246,14 +216,6 @@ Device (SIO) {
IRQNoFlags () {6}
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
IRQNoFlags () {6}
DMA (Compatibility, NotBusMaster, Transfer8) {2}
})
}
#endif
@ -271,12 +233,6 @@ Device (SIO) {
IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
IRQNoFlags () { SIO_INFR_IRQ }
})
Name (_PRS, ResourceTemplate()
{
IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
IRQNoFlags () { SIO_INFR_IRQ }
})
}
#endif
}

View file

@ -37,7 +37,7 @@ MPFR_VERSION=4.1.0
MPC_VERSION=1.2.1
GCC_VERSION=11.2.0
BINUTILS_VERSION=2.37
IASL_VERSION=20220331
IASL_VERSION="R10_20_22"
# CLANG version number
CLANG_VERSION=15.0.0
CMAKE_VERSION=3.24.2
@ -52,7 +52,7 @@ MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
IASL_ARCHIVE="https://github.com/acpica/acpica/archive/refs/tags/${IASL_VERSION}.tar.gz"
# CLANG toolchain archive locations
LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz"
@ -75,7 +75,7 @@ MPC_DIR="mpc-${MPC_VERSION}"
GCC_DIR="gcc-${GCC_VERSION}"
# shellcheck disable=SC2034
BINUTILS_DIR="binutils-${BINUTILS_VERSION}"
IASL_DIR="acpica-unix2-${IASL_VERSION}"
IASL_DIR="acpica-${IASL_VERSION}"
# CLANG toolchain directories
LLVM_DIR="llvm-${CLANG_VERSION}.src"
CLANG_DIR="clang-${CLANG_VERSION}.src"

View file

@ -0,0 +1 @@
560d9e43692e1957bcf24a9bdd663ffe77da88dd tarballs/R10_20_22.tar.gz

View file

@ -1 +0,0 @@
bf8a86addc7fbfa819f1ed2897a0890c42cdcf62 tarballs/acpica-unix2-20220331.tar.gz

View file

@ -192,6 +192,8 @@ detect_special_flags() {
testcc "$GCC" "$CFLAGS_GCC -Wno-address-of-packed-member $FLAGS_GCC" &&
CFLAGS_GCC="$CFLAGS_GCC -Wno-address-of-packed-member"
testcc "$GCC" "$CFLAGS_GCC --param=min-pagesize=1024 $FLAGS_GCC" &&
CFLAGS_GCC="$CFLAGS_GCC --param=min-pagesize=1024"
case "$architecture" in
x86)
;;