From f672d50e2bad1d35e820ab32b76dbf95a7b90a35 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sat, 24 Aug 2019 23:54:41 -0500 Subject: [PATCH 1/4] google/link: fix detection of dimm on channel 1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Patrick Rudolph (cherry picked from commit 4af1fe23f8658ec51380b68ecdd317ddc1dfb854) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35046 Reviewed-by: Angel Pons --- src/mainboard/google/link/romstage.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07cdce..8e8d94335c 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -180,7 +184,10 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(&spd[0], locate_spd(), 128); + memcpy(&spd[2], &spd[0], 128); } void mainboard_early_init(int s3resume) From 7f742241b8116c6c8db80eeefd4189eed4c59160 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 24 Jul 2019 14:30:29 +0300 Subject: [PATCH 2/4] soc/intel/fsp_broadwell_de: Fix use of config_of() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel (cherry picked from commit c9c80c69073bb2677b0b2e58b60fcf93822cb2c7) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35045 Reviewed-by: Martin Roth Reviewed-by: Angel Pons --- src/soc/intel/fsp_broadwell_de/iou_complto.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index c50cbb43c1..f998d97547 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -17,12 +17,14 @@ #include #include #include +#include #define DEVCTL2 0xb8 static void iou_init(struct device *dev) { - const config_t *config = config_of(dev); + /* Use config from device always present in static devicetree. */ + const config_t *config = config_of_path(SOC_DEV_FUNC); u16 devctl2; /* pcie completion timeout From 0802d7b3d19e5db3bfa48141f0bd031399261616 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 2 Aug 2019 20:16:36 -0500 Subject: [PATCH 3/4] drivers/fsp1_1/raminit: fix use of mrc_hob Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs] inadvertently made use of the mrc_hob conditional on CONFIG_DISPLAY_HOBS, when there is no relation between the two, leading to MRC cache data being corrupted. On some devices this caused RAM training to be redone, on others it resulted in a bricked device. Fix this by removing the condition on CONFIG_DISPLAY_HOBS. Test: boot google/{cyan,edgar}, observe third boot and onward do not brick device, properly use mrc_hob via cbmem console and timestamps. Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685 Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) (cherry picked from commit 4183312cec55f00fe22c4dbfd682376e521fc6d3) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35047 Reviewed-by: Patrick Georgi --- src/drivers/intel/fsp1_1/raminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index e71c9a2ddf..21f4ab9b05 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -259,7 +259,7 @@ void raminit(struct romstage_params *params) /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if ((mrc_hob == NULL) && CONFIG(DISPLAY_HOBS)) + if (mrc_hob == NULL) printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { From 789711036aa2072993c769df468f27d291069c72 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 23 Jul 2019 16:47:05 -0500 Subject: [PATCH 4/4] mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove old hda_verb.c code copied from intel/kblrvp7, as it's been superseded by the common block HDA implementation. Fixes a null pointer error preventing the HDA codecs from being initialized, as found in Coverity CID 1403651. Test: build/boot Librem 13v2, verify functional audio Signed-off-by: Matt DeVillier Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) (cherry picked from commit ea244146050e2ea12fd4f9ed1c44693daaac082a) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35048 Reviewed-by: Patrick Georgi --- src/mainboard/purism/librem_skl/Kconfig | 1 + src/mainboard/purism/librem_skl/hda_verb.c | 99 ++++++++++------------ src/mainboard/purism/librem_skl/hda_verb.h | 76 ----------------- 3 files changed, 45 insertions(+), 131 deletions(-) delete mode 100644 src/mainboard/purism/librem_skl/hda_verb.h diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 2372b9d280..ecde9e4774 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -5,6 +5,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index 206af8db7e..ea89f00a53 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation - * (Written by Naresh G Solanki for Intel Corp.) + * Copyright (C) 2019 Purism SPC. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,70 +13,60 @@ * GNU General Public License for more details. */ -#include -#include -#include #include -#include -#include -#include "hda_verb.h" +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x19910269, /* Subsystem ID */ + 0x0000000c, /* Number of jacks (NID entries) */ -static void codecs_init(u8 *base, u32 codec_mask) -{ - int i; + 0x0017ff00, /* Function Reset */ + 0x0017ff00, /* Double Function Reset */ + 0x0017ff00, + 0x0017ff00, - /* Can support up to 4 codecs */ - for (i = 3; i >= 0; i--) { - if (codec_mask & (1 << i)) - hda_codec_init(base, i, cim_verb_data_size, - cim_verb_data); - } + /* Bits 31:28 - Codec Address */ + /* Bits 27:20 - NID */ + /* Bits 19:8 - Verb ID */ + /* Bits 7:0 - Payload */ - if (pc_beep_verbs_size) - hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); -} + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ + AZALIA_SUBVENDOR(0x0, 0x19910269), -static void mb_hda_codec_init(void *unused) -{ - struct soc_intel_skylake_config *config; - u8 *base; - struct resource *res; - u32 codec_mask; - struct device *dev; + /* Pin Widget Verb Table */ - dev = SA_DEV_ROOT; - /* Check if HDA is enabled, else return */ - if (dev == NULL || dev->chip_info == NULL) - return; + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), - config = dev->chip_info; + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - /* - * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, - * 3:I2S Ports. In HDA mode where codec need to be programmed with - * verb table - */ - if (config->IoBufferOwnership == 3) - return; + /* Pin Complex (NID 0x15) */ + AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), - /* Find base address */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (dev == NULL) - return; - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) - return; + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "HDA: base = %p\n", base); + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), - codec_mask = hda_codec_detect(base); + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), - if (codec_mask) { - printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); - codecs_init(base, codec_mask); - } -} + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_skl/hda_verb.h b/src/mainboard/purism/librem_skl/hda_verb.h deleted file mode 100644 index 660ad0c10c..0000000000 --- a/src/mainboard/purism/librem_skl/hda_verb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef HDA_VERB_H -#define HDA_VERB_H - -#include - -const u32 cim_verb_data[] = { - /* coreboot specific header */ - 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ - 0x19910269, /* Subsystem ID */ - 0x0000000c, /* Number of jacks (NID entries) */ - - 0x0017ff00, /* Function Reset */ - 0x0017ff00, /* Double Function Reset */ - 0x0017ff00, - 0x0017ff00, - - /* Bits 31:28 - Codec Address */ - /* Bits 27:20 - NID */ - /* Bits 19:8 - Verb ID */ - /* Bits 7:0 - Payload */ - - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */ - AZALIA_SUBVENDOR(0x0, 0x19910269), - - /* Pin Widget Verb Table */ - - /* Pin Complex (NID 0x12) */ - AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), - - /* Pin Complex (NID 0x14) */ - AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), - - /* Pin Complex (NID 0x15) */ - AZALIA_PIN_CFG(0x0, 0x15, 0x04214020), - - /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* Pin Complex (NID 0x18) */ - AZALIA_PIN_CFG(0x0, 0x18, 0x04a19040), - - /* Pin Complex (NID 0x19) */ - AZALIA_PIN_CFG(0x0, 0x19, 0x90a70130), - - /* Pin Complex (NID 0x1A) */ - AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), - - /* Pin Complex (NID 0x1B) */ - AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), - - /* Pin Complex (NID 0x1D) */ - AZALIA_PIN_CFG(0x0, 0x1D, 0x40548505), - - /* Pin Complex (NID 0x1E) */ - AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), -}; - -const u32 pc_beep_verbs[] = { -}; -AZALIA_ARRAY_SIZES; -#endif