Commit graph

7 commits

Author SHA1 Message Date
Martin Roth
407c7d0da3 Documentation: Add Device Operations
Change-Id: I3ed78f8ce50bb3914f55b2cbb7f5eb668706949a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87202
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-05-09 14:15:15 +00:00
Martin Roth
20d7eaeb0f Documentation: Add chip operations
Change-Id: I5373eab2de2e255f9e3576794b9ad02d9711a6c2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87201
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-05-09 14:15:08 +00:00
Felix Held
010cfa2842 doc/internals/devicetree_language: multiple segment groups supported
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.

Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2025-04-08 19:07:13 +00:00
Felix Held
b8ea245e12 doc/internals/devicetree_language: describe I2C identifier
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.

Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2025-04-08 19:07:02 +00:00
Felix Held
3c7f78e1e7 doc/internals/devicetree_language: eSPI doesn't support legacy DRQ
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.

The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."

Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2025-04-08 19:06:57 +00:00
Martin Roth
712dfc1759 Documentation/internals: Add devicetree language documentation
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If868ad9a87cb2903bf144996fe3b87d29d4fc755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2025-04-06 20:37:46 +00:00
Martin Roth
44921d386c Documentation/internals: Add devicetree documentation
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2a43a96911844bd2b682004d5423126ad00a4bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2025-04-06 20:37:34 +00:00