thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and
the lock hotkey (KEY_COFFEE) on scancode 0x02.
On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2
and Fn-F3 are different from the default one so a new layout has to be
defined.
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add EC ACPI reporting of current temp and platform critical temp.
Adapted from ACPI dump of ODM AMI firmware.
TEST: check reporting of current/critical temps via lm-sensors
from ACPI on Librem 13v1 and 13v4 boards.
Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Serves two purposes:
(1) On some platforms, FSP initialization may cause a reboot.
Push clearing the recovery mode switch until after FSP code runs,
so that a manual recovery request (three-finger salute) will
function correctly under this condition.
(2) The recovery mode switch value is needed at BS_WRITE_TABLES
for adding an event to elog. (Previously this was done by
stashing the value in CBMEM_ID_EC_HOSTEVENT.)
BUG=b:124141368, b:35576380
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I30c02787c620b937e5a50a5ed94ac906e3112dad
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set CPU ID and cores to EC then EC will adapt power table
according to the CPU ID and number of cores.
BUG=b:148126144
BRANCH=None
TEST=check EC can get correct CPU id and cores.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new functions to get (from the EC):
1) The number of USB-PD ports
2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS)
BUG=b:146506369
BRANCH=none
TEST=Instrumented calls to these and verified the data
Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The new host command provides these static capabilities of each USB-PD port:
1) Port number
2) Power role: source, sink, dual
3) Try-power role: none, sink, source
4) Data role: dfp, ufp, dual
5) Port location: these come from power_manager
BUG=b:146506369
BRANCH=none
TEST=compiles
Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add new mailbox command support. Set CPU ID and cores to EC.
EC will according to different CPU to set different power table.
BUG=b:148126144
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I135d2421d2106934be996a1780786f6bb0bf6b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
The firmware configuration (fw_config) field is store in the CBI EEPROM
and it should be used to make firmware customization instead of
sku/variant id.
BUG=b:145519081
TEST=builds
Change-Id: I790998a29e724ecdff8876cca072267537b7cea6
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy ec_commands.h directly from Chromium OS EC repo at sha e57217a250.
This is needed for the FW_CONFIG CBI field definition.
Change-Id: Id010721033ebe32ac9c9482d666cf790442a26ee
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
IMD provides support for small and large allocations. Region IMD Small memory is 1 KB
with 32 Bytes alignment, this region holds smaller entries without having to reserve a
whole 4 KB page. Remaining space is assigned to IMD Large to hold various regions with
4 KB alignment.
The UCSI kernel (kernel version 4.19) driver maps the UCSI_ACPI memory as not cached.
Cache mapping is set on page boundaries and all IMD Small is within the same page.
If another driver maps the memory as write-back before the UCSI driver is loaded then
the UCSI driver will fail to map the memory as not cached.
Placing UCSI_ACPI in IMD Large region will prevent this mapping issue since it will
now be located within its own page. This patch will force UCSI_ACPI region to be
located in IMD Large region.
BUG=b:144826008
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Id00e76dca240279773a95c8054831e05df390664
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All other messages in `ec/lenovo/h8` are prepended with *H8*, so also prepend
the EC version log message with *H8*.
EC Firmware ID 79HT50WW-3.4, Version 7.01A
No CMOS option 'usb_always_on'.
H8: BDC detection not implemented. Assuming BDC installed
H8: WWAN detection not implemented. Assuming WWAN installed
No CMOS option 'fn_ctrl_swap'.
Change-Id: Ib4f341946a336b57bd96c053a05364276caad1ac
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.
This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.
Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.
BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.
Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power
limits to reasonable defaults and can wedge the AP by browning out at
the end of vboot.
BRANCH=none
BUG=b:146165519
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node]
moved the PS2K ACPI device from under the SIO device to under
the LPCB, and while this fixed the keyboard under Windows for
Skylake devices, it was insufficient for Baytrail and Braswell
devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional
under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW,
BYT, SKL, BSW, and KBL platforms, verify keyboard functional
under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI methods to the Wilco EC for controlling a privacy screen
on the device.
BUG=b:142237145, b:142656363
TEST=none
Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the traditional POSIX stdbool.h definitions out from
stdint.h into their own file. This helps for using these definitions in
commonlib code which may be compiled in different environments. For
coreboot everything should chain-include this stuff via types.h anyway
so nothing should change.
Change-Id: Ic8d52be80b64d8e9564f3aee8975cb25e4c187f5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.
Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.
Tested on X200. Testing on other affected targets may be necessary.
Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate.
Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All of the EC_EVENT_* macros can be replaced with the EC_HOST_EVENT_*
macros defined in ec_commands.h, which is synchronized from Chromium OS
ec repository.
BRANCH=none
BUG=none
TEST=emerge-kukui coreboot
Change-Id: I12c7101866d8365b87a6483a160187cc9526010a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Quite a few new functions added here in order to support the use-case
of performing EC software sync within coreboot.
Most of these functions are related to retrieving the EC's hash, and
writing a new image into the EC's flash.
BUG=b:112198832
BRANCH=none
TEST=With whole patch series, successfully performed EC software sync
Change-Id: I0d3c5184dbe96f04b92878f2c19c7875503a910a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change all uN integral types to uintN_t. Make the names of host
command params/responses consistent. Use static struct initialization
to ensure all fields are initialized.
BUG=none
BRANCH=none
TEST=compiles
Change-Id: Ibe1e29e88975c85eea215adedc5f5e483243e0d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36264
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: Ieb54664a6528ce67634991f64a5f3c411822cdf4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36260
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows to read and set bits in the EC ram in the bootblock or
verstage. This can be useful if one needs to read a keyboard key as an
input for get_recovery_mode_switch in vboot.
Change-Id: I20b2264012b2a364a4157d85bfe5a2303cc5e677
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Don't set a default bus type for the Chrome EC on x86. The platform
must select the bus, typically LPC or ESPI.
BUG=b:140055300
TEST=Build tested only
Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's been some time and there are 1420 new commits. Including one that
allows reproducible builds \o/ and one that breaks building with empty
$(CC) :-/
Change-Id: I5e81d5a2f1018481b9103fc5a1f4b8c72fb9deec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30679
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fastboot support in vboot_reference is unused, unmaintained, and
produces compile errors when enabled. Since there is no current
or planned use cases for fastboot, remove it.
BUG=b:124141368, chromium:995172
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35002
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel platforms using eSPI EC communication have just been enabling
the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically
the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
After ChromiumOS CL:1293132 and CL:1295890, Chrome EC can store the flag
telling if the last reboot was triggered by AP watchdog for some boards
(e.g., Kukui).
This CL adds a new function google_chromeec_get_ap_watchdog_flag(),
which reads the AP watchdog flag from Chrome EC, and updates the tables
of reset causes and reset flags.
A new Kconfig option CHROMEOS_USE_EC_WATCHDOG_FLAG is added for
elog_handle_watchdog_tombstone() to determine if watchdog reset was
triggered by the AP watchdog flag from EC instead of the tombstone in
AP.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=test with https://review.coreboot.org/c/coreboot/+/31843
Change-Id: I7a970666a8c6da32ac1c6af8280e808fe7fc106d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Copy ec_commands.h directly from ChromiumOS EC repository (CL:1520574).
Since ec_commands.h already defines usb_charge_mode and only
USB_CHARGE_MODE_DISABLED is used in coreboot, enum usb_charge_mode is
removed from ec.h.
To avoid redefinition of the BIT macro, #ifndef check is added to
include/types.h.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=emerge-kukui -j coreboot
Change-Id: I7ed5344fc8923e45e17c3e2a34371db6f80b079d
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
google_chromec_get_event() depends on the main copy of EC which is
used by ACPI subsytem in the kernel for querying events.
google_chromeec_get_event() also clears the event from EC. Thus if the
kernel has to identify the wake source, it has no way to do that. Thus
instead depend on events_copy_b to log the wake source. Please look at
go/hostevent-refactor for more info.
BUG=b:133262012
BRANCH=None
TEST=Hack hatch bios and make sure hostevent log is correct.
Change-Id: I39caae2689e0c2a7bec16416978877885a9afc6c
Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For files built in ramstage and smm -classes, testing
for !__PRE_RAM__ is redundant.
All chip_operations are exluded with use of DEVTREE_EARLY
in static devicetree, so garbage collection will take care
of the !__SMM__ cases.
Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
