This changes the location to be expressed as a combination of ORs. This
allows aliases for special locations.
For example, `AZALIA_REAR_PANEL` is easier to read than
`AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`.
References:
- Intel High Definition Audio Specification, rev. 1.0a, page 180,
Table 110. Location.
Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
We were keeping 2 copies of the same thing (albeit there were some
slight differences). As azalia_device.h is used much more in the
codebase this was kept as the base and then some of the nice features
of azalia.h were incorporated.
The significant changes are:
- All enum names now use the `AZALIA_` prefix.
This also drops the AzaliaPinConfiguration enum as it was never used
since added in 2013.
Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
As a result of hardware changes on this board, the PHY previously
routed to the PSE GbE 1 is now routed to PSE GbE 0 on the Elkhart Lake
SoC.
This patch changes the device PCI ID in the board's devicetree and
accordingly, the GPIO configuration.
BUG=none
TEST=Boot into Linux and observe whether both PSE GbE 0 and PCH GbE
are working, while PSE GbE 1 remains inactive (not listed by 'ip link')
.
Change-Id: I322371f944d15134e6f48ecd84a4026c2fced27b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The currently used panel type could work with 500 ms but increasing
the value to 1 second allows to use a wider range of LVDS LCD panels,
as many of them specify the delay of 1 s as minimum.
The patch has already been made for mc_ehl3 and serves the purpose of
standardization.
commit c0221aa980 ("mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power
delay to 1 s")
Change-Id: Ife26ff27b41298ceeed7d9aed0c1ae5553ab5ff8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infracture instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I11c3c45eae0e1451d5c54c17b7e60300dedda8fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus
interface is per default write-protected in FSP. This avoids that an
SPD-EEPROM on a DRAM module gets overwritten by the host.
On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM
available. Nevertheless, there is a general purpose EEPROM on the same
address available which needs to stay writeable.
This patch disables the default-enabled write protect feature for the
SPD-EEPROM addresses just for mc_ehl1.
Test=Boot into Linux and make sure a write access into the EEPROM is
possible.
Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
With the latest hardware revision of both mainboards, native function
two of GPIO B23 (PCHHOT_N) is used for diagnostic purposes.
BUG=none
TEST=Checked output verbose GPIO debug messages
Change-Id: Ibe130b5d4c74576294183221765c5f4db9b5ec2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78962
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.
Change-Id: Ic199a60013ceedfd15b191a5fe707be6654ad3a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75078
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The connected panel on this mainboard gets the PWM frequency directly
from the Elkhart Lake CPU. The PWM controls the brightness of the
backlight. Therefore, it is necessary to activate the PWM passthrough
mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide -
5. Configuration Registers).
Link to PTN3460 Programming Guide:
https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf
BUG=none
TEST=Boot into Linux and change the brightness of the screen
Change-Id: Ia0a329426e585b6243c8888806befbe4f6ec2998
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
The connected panel on this mainboard gets the PWM frequency directly
from the Elkhart Lake CPU. The PWM controls the brightness of the
backlight. Therefore, it is necessary to activate the PWM passthrough
mode in the PTN3460 eDP-to-LVDS bridge (see PTN3460 Programming Guide -
5. Configuration Registers).
Link to PTN3460 Programming Guide:
https://web.archive.org/web/20230908074244/https://www.nxp.com/docs/en/application-note/AN11128.pdf
BUG=none
TEST=Boot into Linux and change the brightness of the screen
Change-Id: Iec9d8ae22fced40c45e5bfa8989ad655a722d7ef
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77702
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board uses soldered down LPDDR4, so process their SPD files, and add
the SPD for Micron MT53E512M32D1NP-046WTB provided by Micron.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I978b7450b106b86eef322df8b33df41e038599eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77349
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.
Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
With the latest hardware revision, the polarity of GPP_B5 has been
changed. For a full-populated DRAM configuration, the input signal is
now connected to 3.3 V and for a half-populated configuration it is
connected to ground.
BUG=none
TEST=Use different populated mainboards and check coreboot log
GPP_B5 = 0:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
GPP_B5 = 1:
[DEBUG] 2 DIMMs found
Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO GPP_B5 is used as input on this mainboard. For a full-populated
DRAM configuration, the input signal is connected to ground and for a
half-populated configuration it is connected to 3.3 V.
BUG=none
TEST=Use different HW configurations and check coreboot log
GPP_B5 = 0:
[DEBUG] 2 DIMMs found
GPP_B5 = 1:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There can be mainboard variants, which are only equipped with
half-populated DRAM. For this reason, the meminit parameter for
populatation should be adjustable. The default setting remains at
full-populated DRAM. At mainboard variant level a different selection
via individual input paths can be made.
Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been decided not to use any of the USB 3.0 ports on this board.
This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").
BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.
Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the previous instruction the complete register was set to '0'.
Correctly, only the bits 23:16 must be masked.
Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3
refers to SATA port 1 only. To make this clear, change the name of the
define from 'TX_DWORD3' to 'TX_DWORD3_P1'.
Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.
Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.
Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been decided not to use the USB 3.0 port 1 on this board anymore,
so disable it also with the corresponding USB 2.0 lane.
BUG=none
TEST=USB 3.0 port 1 not functional anymore after boot, while others
continue working.
Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.
Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as
the margin is not big enough. Limit SATA speed to Gen 2 to achieve a
more robust SATA connection.
Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add devicetree and Kconfig entries to enable additional configuration
of the Pericom PI7C9X2G608GP PCIe switch on this board variant.
The amplitude is being adjusted to 425 mV and de-emphasis level to
6.0 mV.
BUG=none
TEST=Read out the PCIe config space values of the switch and check if
they match with the ones configured over SMBus.
Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.
Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This mainboard contains in addition to its base variant, mc_ehl2, an LCD
panel driven through the PTN3460 eDP-to-LVDS bridge.
This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c.
BUG=none
TEST=Boot with the LCD panel attached and observe whether the picture is
stable and free of artifacts coming from wrong resolution and timing.
Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is based on mc_ehl2. In a first step, it contains a copy
of mc_ehl2 directory with minimum changes. Special adaptations for
mc_ehl5 mainboard will follow in separate commits.
Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ia8b7f997ca6234add569da751e1070144790e258
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
An underscore has crept into the mainboard model option for mc_ehl3 and
mc_ehl4 by mistake. This patch fixes the incorrect entry.
Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since commit 833bb448c5 ("mb/siemens/mc_ehl: Remove spd.bin from
CBFS"), the subdir 'spd' is no longer necessary.
Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The support for a spd.bin from CBFS was removed for all mc_ehl boards in
commit 833bb448c5 (mb/siemens/mc_ehl: Remove spd.bin from CBFS).
There is still a remaining comment in romstage_fsp_params.c referring to
the removed capability. This fix removes the spd.bin related part of the
comment to stay consistent with the code.
Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard has SD slot available and therefore it should be enabled.
Use the same SD card configuration as for mc_ehl2 mainboard.
Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard has the RTC RV-3028-C7 connected to the I2C1.
TEST:
- Console Log shows no errors for RV-3028-C7 during I2C1 init
- Finalize device for I2C 00:52 shows correct date and time
Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the USB settings, suitable for this mainboard.
Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).
Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must
be adjust according to the circuit diagram for this mainboard.
Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
