The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because USB Bluetooth takes around 200ms to initialize after the
GPIO is enabled.
Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PS0 and PS3 methods that return the Bluetooth power
resource. This allows the OS to turn on or off the device.
This fixes and issue where the Bluetooth reported a power
failure in device manager.
Change-Id: I0e37fc0369b1dc2b166f851daa183b145a09eb32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86507
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_PR3 should return resources required for the device to be in D3Hot
for which the Intel Bluetooth needs none, so remove it.
Change-Id: I65f206899affd46d791c2ba39235a1af320395d2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't attempt any GPIO operations of there isn't a reset
GPIO specified.
Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Whilst the GPIO's used for Intel Bluetooth should always be consistent
as to whether they're active high or active low, adjust the driver to
pass the GPIO as a pointer, so that it can correctly account for
polarity.
Change-Id: Ib481d49d536b702fef149af882209501c61de6da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: I6d9d6d3b765bba918c08f64458bd1fdad18eff18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86505
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: Ia46eaa8746bcff5a57831c14a2845139116b01da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This method only returns a package, so it does not need to be
serialized.
Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86503
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The scope should be closed with `acpigen_write_scope_end`, rather
than `acpigen_pop_len`.
Change-Id: I80df2ee1b51d7dbba85e556bee0fd7513ac933bb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86500
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not needed as they are controlled via a power
resource that is specific to Intel Bluetooth.
Change-Id: I8502d03db3d43385ac19bc3c17a79232bde1aa94
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add GBTR Method, which gets the state of the RF Kill pin. Unlike
the VGPIO, this can be used for both CNVi and full PCI wireless
cards.
Change-Id: I8d025f63192218399b8d5e60e847853e54a8353c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Move BTRK to \_SB.PCI0 so that the CNVi driver can correctly
access it.
Change-Id: I044b745dce41c9d7a86384b42543ad93485d85ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84990
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`acpigen_soc_get_tx_gpio` will put the result into Local0, rather than
emitting it as a byte so adjust the function accordingly.
Change-Id: I13263d479d1a4520abaf1b6b38514d021e7d4dc9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
This resource is applicable to S0, as it can be used to reset
the wireless and for RTD3, so change it from S5.
Change-Id: I9ae710ef452c717ec414324d2847bf3218fd62d3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Adjust the DSM to return 0x00 (unsupported) when no reset gpio
is passed to the driver. Leave the _RST method to comply with
the ACPI specification but omit the BTRT method as it won't do
anything.
Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Linux has never supported this feature, and according to our FAE, the
Windows driver dropped support for it in 2022 so remove it.
Change-Id: I4f0b6108bb5db657490a8b9395bb99378fc63c4d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add support for RTD3 for Intel Bluetooth. This is done by
controlling the enable GPIO (GPP_VGPIO_0 for most SOCs) that
exists on all wireless cards since Jefferson Peak.
The exception is GalePeak2, which uses VSEC and this driver doesn't
support that.
Change-Id: Ibea97ab0ae0a9f1eb6aaca43d831bb4ce7bdc02e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Add AOLD Method, which returns an integer based on
whether Audio Offload is enabled. Leave the existing
control of Audio Offload in `soc/soc_chip.h`. Add
`cnvi_bt_audio_offload` in the USB ACPI `chip.h` to
control the aforementioned return value.
The value in `soc/soc_chip.h` and `chip.h` should
match.
Change-Id: Idb804fb1cf0edef4a98479a6261ca68255dbf075
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84134
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since version 6.6, Linux has warned about the lack of a
_PRR Method being available for Intel Bluetooth. Add one
that follows the recommendations from Intel in their
connectivity integrated guide, that uses the reset
delay set by the DSM.
Change-Id: I9c7fd286e8630d77d79d1d7cd113ce3a3d3d0fe3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84145
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel Bluetooth driver can be combined with either CNVi, or
full PCI wireless cards such as the AX210. Move it to the USB
code so it can be used by either or.
Change-Id: Ib456b1870501182b2d8788e5d53bbf4d7981f91b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84627
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code for Intel Bluetooth is unrelated to all other devices, and
needs to grow in size - move it to another file.
Change-Id: I65ccb9f2fd95b07fa63866485920539adc474873
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84625
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Power Resource for Intel Bluetooth, that can reset
the Bluetooth using the delay configured in the DSM.
Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for creating a DSM Method for Intel Bluetooth that
is outlined in Intel's connectivity integrated guide (which has
no document number).
It supports two GUIDs:
Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Tile Activation
Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9)
BIT(0) Indicates whether the device supports other functions
BIT(1) Set Bluetooth reset timing
Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8cf3d2e2cd1b6ebe4e941ad64f27698379fef696
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80080
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
This is controlled via a Kconfig option.
TESTED: works on qemu x86, arm and aarch64 with and without VBOOT.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the drivers directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Instead of adding the new PCI IDs of the XHCI controllers in every new
chip generation to the pci_xhci driver, bind the driver to the internal
PCI devices of the XHCI controllers via the device ops statement in the
chipset devicetree. The PCI device function of the XHCI2 controller in
Mendocino can be either a dummy device or the XHCI controller, so the
device ops are attached to that device in the mainboard devicetree
instead. The Glinda code is right now just a copy of the Mendocino code,
so it'll change in the future, but for consistency the equivalent
changes to those in Mendocino are applied there too.
Since the device ops are now attached to the devices via the static
devicetree entry, also remove both the xhci_pci_driver struct and the
amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c.
TEST=SSDT entries for the XHCI controllers are still generated on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Hook up xhci ops for Phoenix xHCI device. Benefit is we don't have to
bother by adding xhci DID.
BUG=b:285981912
TEST=check coreboot log shows below.
[INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB)
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib59874948725966b04b54def3f6de463afeda709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The WCH CH347 presents a USB CDC serial port on interface 4 while in
operating modes 0, 1, and 3. Mode 0 also presents a UART on interface
2 but this is ignored for compatibility with the other modes. Mode 2
uses vendor defined HID usages for communication and is not currently
supported. Like the FT232H the data format is hard coded to 8n1.
Tested using a CH347 breakout board and a Dell Latitude E6400.
Change-Id: Ibd4ad17b7369948003fff7e825b46fe852bc7eb9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68264
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Using malloc would increase the heap use each time this function is
called. Instead allocate a per struct device buffer inside the
chip_info struct.
Found by coverity scan, CID 1488815.
Change-Id: Ie24870b34338624b3bf3a6f420debdd24a68ffbd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64338
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add chip driver for soldered down external USB hub. This driver adds
ACPI objects for the hub and any downstream facing ports.
BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the hub and any
configured ports have ACPI devices defined in SSDT.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I11d7ccc42d3dce8e136eb771f120825980e5c027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63968
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers
are enumerated successfully and ACPI device objects are added in SSDT.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the member `use_gpio_for_status` to the structure
`drivers_usb_acpi_config`, so the `devicetree.cb` can specify it.
This field is then used to initialize the corresponding field in the
structure `acpi_power_res_params` in `usb_acpi_fill_ssdt_generator()`.
The member `acpi_power_res_params::use_gpio_for_status()` is already
being used by `acpi_device_add_power_res()` to determine which version
of the `_STA()` method to output.
BRANCH=None
BUG=b:225022810
TEST=Dump SSDT table for guybrush
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ia9a4b62c857f7362d67aee4f9de3bb2da1838394
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
