coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
`SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
`SOC_INTEL_CSE_SEND_EOP_LATE' is selected
Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.
This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.
This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 1 | 1020.052 | 971.272 |
| 2 | 1015.911 | 971.821 |
| 3 | 1038.415 | 1021.841 |
| 4 | 1020.657 | 993.751 |
| 5 | 1065.128 | 1020.951 |
| 6 | 1037.859 | 1023.326 |
| 7 | 1042.010 | 984.412 |
|----------+----------+-----------|
| Mean | 1034.29 | 998.20 |
| Variance | 4.76 % | 5.21 % |
The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.
We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 0 | 1067.719 | 1050.106 |
| 1 | 1058.263 | 1056.836 |
| 2 | 1064.091 | 1056.709 |
| 3 | 1068.614 | 1055.042 |
| 4 | 1065.749 | 1056.732 |
| 5 | 1069.838 | 1057.846 |
| 6 | 1066.897 | 1053.548 |
| 7 | 1060.850 | 1051.911 |
|----------+----------+-----------|
| Mean | 1065.25 | 1054.84 |
The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.
CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
requested to wait for the command completion before loading the OS or
second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
command and can perform other operations in the meantime as long as
they do not involve HECI commands.
On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post. FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.
If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.
According to commit 387ec919d9 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.
BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post sent soon after FSP-s and EOP message receive at
`BS_PAYLOAD_BOOT'. Verify robustness by injecting a
`GET_BOOT_STATE' HECI command with or without `heci_reset'. The
implementation always successfully completed the EOP before
moving to the payload. As expected, the boot time benefit of the
asynchronous solution was under some injection scenario
undermined by this unexpected HECI command.
Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The patch enables addition of core_type member to 'struct cpu_info' for
Alderlake platform.
TEST=Build and verify the code for Gimble
Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The patch adds new member 'core_type' to the 'struct apic_path' and
updates core type information.
TEST=Build the code for MTL
Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.
Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.
TEST=Able to build and boot google/marasov and crashlog is working.
Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.
Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.
Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.
TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.
Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change to use simple device function for setting PMAX_LOCK because
the Sapphire Rapids PCU device is not scanned during coreboot PCIe
bus scan and would see "PCI: dev is NULL!" failure.
Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.
TEST=Able to build and boot google/taeko where USB wake is working.
Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For some Xeon-SP (such as SPR-SP), more buses should be probed.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC
instead of UBOX_DEV_PMON.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add platform cpu info for known microcode, print cpuid & processor
branding string. This will print as in the following example:
CPU: Intel(R) Xeon(R) Platinum 8468H
CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130
CPU: AES supported, TXT supported, VT supported
Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
FSP may program a different ID under certain circumstances.
Read IOAPIC ID from hardware instead of using some define that
might not reflect how hardware is configured.
Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Having these two functions public allow "asynchronous"
HECI command implementation.
Typically, these function can be use to implement an asynchronous
End-Of-Post.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Successful compilation for brya0
Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The default SPD size is set to 256 bytes, instead of 512 for
LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused
the SMBus libraries to read only the lower half of the DIMM SPD on
protectli/vault_ehl. The lower half of the SPD passed to FSP causes
a bug in DIMM change detection, which relies on the CRC of the
manufacturer bytes in the upper half of the SPD (CRC of zero bytes
always gives zero so no change was assumed). Setting the DIMM SPD size
to 512 fixes it.
Setting the SPD size in SoC will also avoid such problems in the future
Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing
the correct default of 512 bytes is an obvious thing to do.
TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory instead of doing the fastboot with old
DIMM data.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames all references of `top_of_ram` (TOM) in IA common
`basecode` module (for example: functions, variables, Kconfig,
Makefile and comments) with `ramtop` aka top_of_ram to make it more
meaningful and to avoid conflicts with Intel SA chipset TOM registers.
BUG=Able to build and boot google/rex with the same ~49ms savings
in place.
Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To be consistent with other occurrences in soc/intel/common, remove the
return statements of weak void funtions since they are not generally
useful.
Found by the linter.
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Subrata Banik <subratabanik@google.com>
If the host supports CXL, get proximity domain info from FSP HOB. The
proximity domains may include both processor domains and CXL domains.
Add header definition for proximity domain.
Add CXL memory into memory map.
Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
DPR should not be configured for VTD devices of other stacks for
SPR-SP. Such processor(s) would be configured with
SOC_INTEL_MMAPVTD_ONLY_FOR_DPR.
Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
... instead of ME base/limit if the processor is configured with
SOC_INTEL_HAS_NCMEM.
Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This soc utility function can set cmos flag to enforce
FSP MRC training.
Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and
coreboot's romstage requires ~1 KiB, but it is not satisfied currently.
Increase the BSP stack size by the missing 1KiB for romstage like
other SoCs do.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iddd4a4613bc174aec4331732371a27450225258c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Commit 6a6ac1e0b9 ("arch/x86/cpu: introduce and use
device_match_mask") added the device_match_mask element to the
cpu_device_id struct and uses it to be able to mask off for example the
stepping ID when checking for CPU table entry that matches the silicon
the code is running on. Commit 3ed903fda9 ("soc/intel/xeon_sp/spr: Add
Sapphire Rapids ramstage code") added a CPU table that was missing the
device_match_mask which results in this being 0, so the first entry of
the CPU table would match for any Intel CPU which isn't the intended
behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array
element.
Likely all entries could be replaced by one entry that uses the
CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but
that's out of scope for this fix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Programming MTRR happens later in the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath.
fast_spi_cache_bios_region() assumes an existing MTRR solution from
x86_setup_mtrrs_with_detect().
This fixes a problem introduced by 829e8e6 "soc/intel: Use common
codeflow for MP init".
Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the legacy ACPI Processor() object as it only
supports 8bit IDs and thus no more than 255 cores. Use the
new ACPI Device() object that supports more than 255 cores.
Test:
- Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running
384 CPU cores in total.
- Verified on Intel ADL RVP with 20 cores that Linux 5.15 is
still working without errors.
Change-Id: I309c06b6824704c84fd16534655334a6f269904a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
In cases where there are limitations on the connected device behind the
PCIe root port it can be necessary to limit the speed. The FSP parameter
'PcieRpPcieSpeed' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the
vr_config table.
Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.
TEST=Able to build and boot google/rex. GPIO debug print is showing
GPIO PAD config DW1 bit[14:17] are getting programmed.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.
Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.
Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch modifies the serial msg log_level at runtime to highlight
an ERROR if the DIMM count is zero. It would help to draw the
attention while parsing the serial msg and catch any underlying issue.
TEST=Able to see ERROR msg while booting google/rex with FSP v3064
Without this patch:
[DEBUG] 0 DIMMs found
With this patch:
[ERROR] No DIMMs found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some MSRs used in SPR code are common among currently supported
Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs
which have changed are added to SPR's soc_msr.h.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HSPHY firmware must be downloaded to DMA-allowed host address
space. Check for DMA buffer presence and use it as the buffer for HSPHY
firmware to be downloaded from CSME.
TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4
with DMA protection enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new common block with VT-d/IOMMU support. The patch adds an
option to enable DMA protection with PMR. However the payload and
OS must support VT-d in order to properly handle I/O devices.
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
With newer xeon_sp processors, the concept of "north bridge" became
obsolete, instead uncore should be used. Therefore we use uncore_acpi.c
(instead of nb_acpi.c) going forward.
Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Intel Meteor Lake decides to enable early caching of the TOM region to
optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM`
config.
TEST=Able to build and boot google/rex to ChromeOS and reduce the boot
time by 77 ms.
Without this patch:
950:calling FspMemoryInit 936,811 (19,941)
951:returning from FspMemoryInit 1,041,935 (105,123)
With this patch:
950:calling FspMemoryInit 905,108 (20,103)
951:returning from FspMemoryInit 964,038 (59,929)
Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements a module that can store the top_of_ram (TOM)
address into non-volatile space (CMOS) during the first boot and
use it across all consecutive boot.
As top_of_ram address is not known until FSP-M has exited, it
results into lacking of MTRR programming to cache the 16 MB TOM,
hence accessing that range during FSP-M and/or late romstage causing
long access times.
Purpose of this driver code is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).
TEST=Able to build and boot google/rex to ChromeOS.
Without this patch:
950:calling FspMemoryInit 936,811 (19,941)
951:returning from FspMemoryInit 1,041,935 (105,123)
With this patch:
950:calling FspMemoryInit 905,108 (20,103)
951:returning from FspMemoryInit 987,038 (81,929)
Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
