Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch updates the Rex flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.
For default chromeos.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.9MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
Additionally, moved RW_LEGACY under extended BIOS region.
For chromeos-debug-fsp.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.2MB.
RW_LEGACY: Dropped
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
BUG=b:262868089
TEST=Able to enable CSE update on google/rex and have free space
to add one more PUNIT FW for support different SoC stepping.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Debug FSP is ~920KiB larger than release FSP and we don't have
sufficient space for rex flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:262868089
TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP.
Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Having L1.2 enabled on the SD port increases the kernel resume times by
between 30 & 40ms. This patch disables L1.2 on SD to get that time
back.
As with needing to have hotplug enabled on the SD card, this seems like
a driver issue, so hopefully that will get sorted out and this patch
can be reverted.
BUG=b:274025743
TEST=resume times are decreased.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a new port for the Intel DQ67SW desktop board. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
A list of tested working and non-working features is in the
documentation page.
Change-Id: Ifc703f2d0ad45495e71d3f7799347430f5196791
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:275644832
TEST=emerge-dedede coreboot
BRANCH=firmware-dedede-13606.B
Change-Id: I644f3aa3187e08146d78abb70a568833bc9b9211
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Initial hades GPIO config. Combination of original brya basebaord,
Agah and new arbitrage output for hades design.
Also moved GPIO config to the non baseboard variant model as we did on
rex0.
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2a850240dd7f3ddf137d6a2ebe8a147f8976c16b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add early configuration of the GPIOs that control the M2 SSD resets.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I81439d193bdd7296d8a8fea83c5c6be2c75adbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73989
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add option decode for USB-C DDI connection type and remove unnecessary
break after return.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If38fa667daeb2dd176ecdf33abaec9b56d633a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Realtek RTL8111E NIC is currently not defined as a child device,
resulting in the on_board flag not being set to 1. This means that
Linux / udev will call the device enp4s0 rather than eno0, as is
appropriate for on-board ethernet devices.
This patch defines the NIC as a child device of PCIe port 6, so that
it's properly defined as an on-board device.
Change-Id: I2e1b65e4d27852297a739e332c52c15a8c81b858
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74090
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
To avoid having to calculate the length of a struct separately, rework
the code to give the struct a tag name, so that `sizeof()` can be used
instead. This involves refactoring the `get_emi_eeprom_vpd()` function
to return a struct instead of a union, so callers can no longer access
the EEPROM data as an array of bytes without additional code, but this
array view is only used inside `get_emi_eeprom_vpd()` when reading the
data from EMI.
Change-Id: Id1bc40939631baa131b5f60eadbfe42838294ebe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:273791621
TEST=emerge-nissa coreboot
Change-Id: I1a6013e0ad0c430d83bbbad4b92392c8c4815b0d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use die_no_apcb to cause a build error when the APCB or SPD sources are
not found.
TEST=builds with and without matching APCB and SPD sources
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This sets the location of the skyrim MP2 firmware within the mainboard's
blobs directory, and adds the Kconfig option to the mainboard directory
so that it can be enabled in a saved .config file.
The skyrim MP2 firmware is skyrim specific, so it should not be placed
in the main PSP AMD_BLOBS directory.
We will also only want to enable the MP2 firmware for chromeos builds as
it's not useful for non-chromeos builds.
BUG=b:259554520
TEST=Build MP2 firmware into image, see that it gets loaded
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms
between backlight on and vary backlight.
BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table;
measure the power on sequence on whiterun
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 5 (0101)
BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I20a12a58d8a3d66a901a14569ca710acba3c05f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73920
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Set open-drain GPIOs for ChromeOS as input and bias-disable mode.
After applying this patch, the voltage of these pins will become the
expected value 1.8V (previously 1.0V), preventing wrong judgement of
low/high.
Reference document:
MT8188G_GPIO_Formal_Application_Spec_V0.3
BUG=b:274058085
TEST=build pass
Change-Id: I057716df6c59efb84fc395109db022b82ce528c4
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPD usb3_port_force_gen1 for skyrim
The default setting is set to disable
Skyrim -> set default as disable
BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify the setting will be applied on skyrim.
Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set orientation to LB_FB_ORIENTATION_BOTTOM_UP to align the volume
up/down direction with menu up/down in FW screen.
BUG=b:274749478
TEST=see FW screen in portrait mode.
TEST=volume key behaves as expected
Change-Id: If32859c4bf256c97147622ff04a17fc2ec80303d
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enable SBU orientation handling by SoC for both USBC port2 and USBC
port3.
Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't,
they do not flip the data lines, hence we need to set bits for USBC ports.
Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Remove the sleepstates.asl as it was written for SOCs pre-Skylake
and not needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I46fe934c2a50b3d61575f66f0881ab6754fe8dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move EC FW from a CBFS file to an FMAP entry and rename the EC signature
section to EC_SIG.
An offset of (16M - 512K) was chosen to line up the EC FW before the
RW_MRC_CACHE.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9b19d92043790b10acd20fbfdf394d5bd67b8295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Commit 65c456227e (mb/asrock/b75pro3-m: Add CMOS layout/defaults and
vbt.bin) introduced CMOS settings for selecting CPU_FAN{1,2}, but this
code was never implemented. Remove the fake setting for it.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ic2f4aa42f9cfd77defc2a11e16643690356bc26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch drops the UFC sensor OV2740 (reused from the Brya chassis)
support for Rex and added support for Rex specific UFC sensor HI-556W.
BUG=b:269499723
TEST=Verified UFC is working on google/rex Proto 1.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b8ac08adec351a103ac1764d974db4881dc4d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70225
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Atlas stores VPD (Vital Product Data) in an I2C EEPROM, which is only
connected to the EC. In order for the host (x86) to be able to access
the VPD, the EC reads the EEPROM contents into a buffer in EC RAM and
provides the host with read-only access to this EC RAM buffer through
EMI (Embedded Memory Interface) 0.
The VPD layout is designed to be extensible yet backwards compatible.
The code in coreboot uses the revision field to know which fields are
valid, and will populate the rest with fallback values.
Use the serial number and part number in VPD to populate SMBIOS tables.
Change-Id: I2d3d70fee22548daa73ef98af56c98e950dc5e9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Implement initial support for EMI (Embedded Memory Interface), which
Microchip describes as "a standard run-time mechanism for the system
host to communicate with the Embedded Controller (EC) and other logical
components". EMI allows the host to access regions of EC memory without
requiring any assistance from the EC.
For now, Atlas only uses EMI 0. This change enables EMI 0, subsequent
commits will read data from it.
Change-Id: Ia899ae71e97f9fc259397dfb5fb84ca06545f5d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The SKU ID is not really used on Geralt. Both ADC channels 4 and 5 will
be used for LCM ID on derived projects. For Geralt reference board, only
PANEL_ID_LOW_CHANNEL is valid.
BRANCH=none
BUG=b:247415660
TEST=boot Geralt proto0 and see FW screen in DEV mode.
Change-Id: I77a3caadc1b0be5bf39dd2cf73ea1df88f9a09ea
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73874
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Intel Client PCIe* controller expects each device should drive the
SRCCLKREQ#. If the GPIO is set to native mode for a device, which does
not support SRCCLKREQ#, then during RTD3 exit link would not be
established. Because controller samples the SRCCLKREQ# before
detecting the device and break L1 as the system might enter L1SS as
controller detects SRCCLKREQ# as de-asserted.
As a workaround the Pins must not be configured in Native Mode (CLKREQ
native function). Therefore here they are not configured at all.
source: 689882 (intel document ID)
So apparently hardware doesn't sample SRCCLKREQ Pin if it's not
configured as such.
That workaround suggestion however also brought a patch to FSP, which
in turn causes the same bug (even if SRCLKREQ are not configured).
Usually in order to make use of root port power saving features (e.g.
clock gating), the Root port must either be disabled or a CLKREQ Pin
must be configured. The patch however removed that check before
enabling power management for the rootport.
Workaround (until FSP is fixed):
pretend to FSP that the rootports have a CLKREQ Pin attached, by
supplying them in the FSP UPDs. That will cause FSP to configure the
CLKREQ Pin and enable power management for said rootport, but it will
not crash on L1 entry/exit. That has been done on the Atlas board
(as workaround) for a short period of time (before applying FSP Fix)
like this:
// RP 5 (the rootport you want to fix)
- memupd->FspmConfig.PcieClkSrcUsage[2] = 4;
// e.g. choose a clkreq pin that is not routed out
- memupd->FspmConfig.PcieClkSrcClkReq[2] = 0;
Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent
the same issue, but for CPU root ports. If not done the following will
happen in coreboot:
[DEBUG] PCI: 00:06.2 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:06.2
[DEBUG] PCI: pci_scan_bus for bus 02
[DEBUG] PCI: 02:00.0 [1344/5410] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] ASPM: Enabled L1
[EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting
[EMERG] Code: 0 eflags: 00000046 cr2: 00000000
[EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000
[EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100
[EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56
[EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00
This patch is only a workaround for the issue and it will be reverted as
soon as FSP is fixed.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I324bc6ab158d4b3b5ae9d3bade21076b44bc8892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
While doing the initial port of this board, hda_verb.c was mainly put
together by guesswork and borrowing the pinouts from similar boards.
While it was mostly correct, not everything was tested properly.
This change takes the values of vendor BIOS version P1.80, obtained by
running `cat /sys/class/sound/hwC0D0/init_pin_configs` while booted
from the vendor firmware.
7.1 channel audio and front panel audio are now also tested.
Change-Id: I60b0f55c203f42b220f13cf943912f7428476792
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73935
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fabian Groffen <grobian@gentoo.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Most of the code is taken from 2570p, adjusted with autoport, SuperIO
from 8470p and inteltool, GPIO config from inteltool via autoport.
The laptop works well under coreboot with SeaBIOS 1.16.1 payload,
running Debian GNU/Linux with kernel 6.1.15.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I854104516d5b6fbd78ee2989197000a7dbb85136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73856
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As a follow-up to commit 1a591d0c44 (mb/asrock/b75m-itx: Make NIC a
child device below PCIe port 4), this change corrects the subsystemid
being incorrectly applied to the Realtek NIC instead of the PCIe root
port.
Change-Id: Ib6fb8bf808132c008846d8ca9acde0eef277765c
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This board inherited cmos.default and cmos.layout from asrock/h77pro4-m,
which has two CPU fan headers and a CMOS option to select which one will
provide the tachometer source.
However, the code for this was never implemented. Moreover, this board
only has one CPU fan header, rendering the option useless. This change
removes the option from cmos.layout and cmos.default.
Change-Id: Ib4580e243781e2340af2cefb825f26ee896c2bd3
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73931
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Of the 13 mainboards that implement mainboard_should_reset_usb() hook,
all but one do the same: Stop MRC from resetting USB when resuming
from S3 suspend.
This hook turns out is only here to facilitate a USB reset workaround
on samsung/stumpy for an old ChromeOS kernel which is no longer needed.
Drop the workaround, the hook, and headers no longer used.
roda/rv11/early_init.c is left with no useful code after this patch,
so drop it entirely from both bootblock and romstage.
Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The default SPD size is set to 256 bytes, instead of 512 for
LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused
the SMBus libraries to read only the lower half of the DIMM SPD on
protectli/vault_ehl. The lower half of the SPD passed to FSP causes
a bug in DIMM change detection, which relies on the CRC of the
manufacturer bytes in the upper half of the SPD (CRC of zero bytes
always gives zero so no change was assumed). Setting the DIMM SPD size
to 512 fixes it.
Setting the SPD size in SoC will also avoid such problems in the future
Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing
the correct default of 512 bytes is an obvious thing to do.
TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory instead of doing the fastboot with old
DIMM data.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCIE RP 9 on taeko is for eMMC.
Correct the comments to prevent confusion.
BUG=b:271003060
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
It seems like the hotplug enable might be doing more than just enabling
devices to be hot-plugged, so re-enable the feature for the SD card.
Removing it from SD increased resume time and may have caused reboot
issues for SD after resume.
This is a partial revert of CB:73512
BUG=b:273620322
TEST=See resume time go down on Skyrim
BRANCH=Skyrim
Change-Id: I4814d4377d0ba8a1e9b308853b3e02a4a27bd8d5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Enable Frostflow platform to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:274028833
BRANCH=none
TEST=FW_NAME="frostflow" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Change-Id: I6437d5324877702f2f8b4c69d4c850543e1b74be
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73884
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The return statement at the end of the method is never reached. Remove
it. Also while at it, assign the return value of variant_board_sku()
to ski_id while the variable declaration and make it const.
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Change-Id: If05df8934f68ffec9ad21c88394055f71d618133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This will be tracked directly in the bug, so a code comment is not
needed.
BUG=263161283
TEST=none
BRANCH=Skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4d5af35762354c8825d30f813098547a7e009e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73828
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
