As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h") and commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR
from device.h to static.h"), sources that use code generated from the
devicetree should directly include static.h. This allows static.h to be
removed from device.h, eliminating many unnecessary dependencies on the
devicetree for objects that only need the device types and function
declarations.
Add static.h to the includes of all remaining files that require static
devicetree access through config_of_soc(), the sconfig generated names,
or DEV_PTR().
Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84591
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC-
related functions to avoid needing type casts in the callers. This also
allows dropping the VIO_APIC_VADDR define and consistently use the
IO_APIC_ADDR define instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I912943e923ff092708e90138caa5e1daf269a69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Multiple links are unused throughout the tree and make the code more
confusing as an iteration over all busses is needed to get downstream
devices. This also not done consistently e.g. the allocator does not
care about multiple links on busses. A better way of dealing multiple
links below a device is to feature dummy devices with each their
respective bus.
This drops the sconfig capability to declare the same device multiple
times which was previously used to declare multiple links.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iddac15cc42532f44dda44032be0f8525f6347abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80070
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This reverts commit acbc491237.
Reason for revert: CB:79525 fixes the issue that led to the revert
by not maintaining the heap in the SMM-stored copy of ramstage at all.
Change-Id: I3c8ef785486d275c9341859d34fce12253bd2bb9
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80023
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial support for multiple PCI segment groups. Instead of
modifying secondary in the bus struct introduce a new segment_group
struct element and keep existing common code.
Since all platforms currently only use 1 segment this is not a
functional change. On platforms that support more than 1 segment the
segment has to be set when creating the PCI domain.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
There's neither need to remove get_hw_mem_hole_info from the code if the
Kconfig option was set to 0 nor the actual value didn't make any
difference in the behavior of the code: When node_id has still its
initial value of -1, domain_read_resources won't use the value of
hole_startk, and when node_id is set to 0, get_hw_mem_hole_info also
sets hole_startk to the actual value that then gets used by
domain_read_resources.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieffab695a3151ed7f6bf9d6c880bbb43eecf7893
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79609
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node, so the nodeid parameter of
get_node_pci is always 0. Since this SoC has a chipset devicetree, we
can just use DEV_PTR(ht_X) instead of the pcidev_on_root call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bf9d214b4c2e5d995976fb79fef6fe43a6e9fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node and since we're in ramstage when
domain_read_resources gets called, there's DRAM on this node, so no need
to check for this. To be extra sure, also initialize basek and limitk
before calling get_dram_base_limit with pointers to those as arguments.
This won't be necessary for the code to work as intended, but will
probably keep the compiler from complaining. Also move the declaration
of basek, limitk and sizek to the beginning of the function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ef8011eb57b16218b8f5fea295900b855c3014b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79611
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Start with the resource index 0 and increment it after reporting each
resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6fb59ff3d371b744b53093d17392d1c3510bef82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This APU is always a single-node and also only has one DRAM controller,
so there is only one valid DRAM base and limit register. It's also worth
mentioning that the assumption made in get_dram_base_limit that the n-th
node is using the n-tn DRAM range register was valid for K8, but not
necessarily on newer generations than that.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0529c66e8d0e6c8eb42eec2c6d9d2e892287865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79607
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This APU is always a single-node and also only has one DRAM controller,
so we don't need to loop over the different nodes to find the memory
hole below 4GB. We also don't need to check for the special case where
the memory hole is non-DRAM address space between the parts of the
address space decoded by different DRAM controllers.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9793d911d2d496be49168c06d83ceb802bc2b647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This APU is always a single-node, so domain_read_resources only needs to
handle exactly one node and doesn't need to loop over the nodes.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4218077cb4e11b762ce0e8694a97bdec33eaa056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This SoC only supports a single-node configuration, so all the code
related to multi-node support can be removed. In this commit only the
get_fx_devs function and related code are removed for better
reviewability. In f1_write_config32 it's no longer needed to loop over
the different devices of the different nodes, so only a single PCI
config space write remains.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dc7324d3fcd0d07ac7a3a246a740fd9e91c3840
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79604
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node system and bits 4..6 of the node ID
register D18F0x60 are also marked as reserved in BKDG #52740 Rev 3.05.
On an APU2 board with quad-core APU, this register reads back 0x00030000
which results in a value of 1 to be returned from get_node_nums, so this
patch doesn't change behavior, but stops using reserved bits.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65ed1124c0ca8e7eba54ff53dc626d35cd5e2e58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79603
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This system only has one northbridge and amd_initcpuio has already set
up the routing of the legacy VGA IO and MMIO ranges to it. Since only
the pci_dev_set_resources call remains in nb_set_resources, use
pci_dev_set_resources directly as set_resources function.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3835db9fd83221ac2b8e34d998f938812d24413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since the IOMMU is always function 2 of device 0 on bus 0, the device
operations can be statically assigned in the devicetree and there's no
need to bind the IOMMU device operations to the PCI device during
runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since the northbridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the northbridge device operations to the PCI
device during runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Function 0 of the device that has the bridges to other buses is a dummy
function that can be left enabled to not have to shuffle around the
device function numbers when the first PCI bridge on that device isn't
enabled. That dummy device function is however not a PCI host bridge, so
change the comment from 'Dummy Host Bridge' to 'Dummy device function'.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79397
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is likely a copy-paste leftover, since this SoC neither has a PCI
device with the device ID 0x1200 nor is family 10h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7095f208a7503545ea012241d058692a510109f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79094
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since this chip is a SoC and also to bring the chipset devicetree more
in line with the chipset devicetree of Sandy Bridge, merge the chip
operations of the northbridge's root complex and the northbridge itself
into one chip operations structure and use it at the top level of the
devicetree.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI
devices. The HDA controller in the FCH at function 2 of device 0x14 on
bus 0 was missing in the mainboard's devicetrees.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 44a48ce7a4.
Reason for revert: It breaks wakeup from suspend on a bunch of boards.
While this approach of eyeballing "correct" values by chipset _should_
be fixed, it should also be accompanied by compile time verification
that the memory map works out.
Since nobody seems to care enough, let's just revert this, instead of
keeping the tree broken for a bunch of configurations.
Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
We have a tiny HEAP_SIZE by default, except when we don't, and
mainboards that override it, or not.
Since memory isn't exactly at a premium these days, and unused heap
doesn't cost anything extra, just crank it up to the highest value
we have in the tree by default and remove all overrides.
Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of open coding this, use the mmio_range helper function to tell
the resource allocator about the northbridge's IOAPIC's MMIO. This
change sets the IORESOURCE_RESERVE and IORESOURCE_STORED bits in the
resource flags that weren't set before, but mmio_range is already used
elsewhere for similar purposes.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66a73cdb22fd551e4359914ba5513313dcc3193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
TEST=APU2 still boots and doesn't show any new errors in dmesg.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
In soc/amd this function is unused so drop it and rename
_acpi_fill_ivrs_ioapic().
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Replace the magic constants by using defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie558de02cd4f8914409639a74c54b57df3418ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75665
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the
scope for the CPU objects and patching this SSDT in coreboot to use the
\_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the
\_SB_ scope instead by setting the late platform configuration option
ProcessorScopeInSb to true.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I411201b55cfee30ae41da4e6814679bdb49e9bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73386
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d71928 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
back from Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e724292431be7f7c2a0b6678b426831e3c19154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in
line with get_top_of_mem_below_4gb.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of
open-coding the functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and
get_top_of_mem_above_4g to make it clearer what those functions return.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.
Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.
For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.
Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Read IOAPIC ID and number of interrupts from programmed registers.
Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.
Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
