Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
mp_init_with_smm returns cb_err type, where 0 means success and
negative values represent error (see cb_err.h).
However, failure checks in form of "ret < 0" is not
straightforward. Use "ret != CB_SUCCESS" instead.
Change-Id: I7e57f2da0361f3109051e9a35b1cce81d559b261
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The original code uses TRE0-TRE3 register to determine whether or not
the TBT controller exists. However, there is a remap in fsp could confuse
the TRPx._STA.
Ex:
Disable TBT controller 0 on b:0 d:7 f:0
Enable TBT controller 1 on b:0 d:7 f:1
The FSP will do the remap and after the remap:
TBT controller 1 is on b:0 d:7 f:0
TBT controller 0 is on b:0 d:7 f:1
This is becuase func 0 must exist per pci spec.
However, the TRE0-TRE3 will not be remapped so that the ACPI
TRPx._STA method could be confused.
In such scenario, TRP0._STA will return 0x0, TRP1._STA will return
0xf which is wrong because TBT controller 1 is now at b:0 d:7 f:0
TEST=tested on rex and _TRPx._STA returns correctly. TBT function OK
Change-Id: I54f2ea99cd1ec73dd0b71a6ba738aa927b0ae80f
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The TBT PCIe devicetree settings are not remapped properly when
TBT PCIe port 0 is disabled.
This code refer SHA:58bc5d937 to remap the PCIe devtree settings
properly in case of TBT PCIe port0 is disabled,
TEST=Tested on screebo and found "Remapping PCIe Root Port #2 msg"
showed up in coreboot log
Change-Id: I7c7549ddf8ccdd67d7af7c69f51a84614cff9a03
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81841
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename different spd_raw_data[] for DDR3 and DDR4.
This is to solve the conflict when we include both "ddr3.h" and ddr4.h"
for example here: src/device/dram/spd.c.
Otherwise, it won't compile as DDR3 and DDR4 have different
spd_raw_data[] size.
Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When microcode is not found, intel_microcode_find() will output warning
and skip the update. Remove the duplicated warning in CPU codes.
TEST=Build and boot on intel/archercity CRB
Change-Id: I0264edc01e90186a7b77d57f9c147d3b73747437
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update a simple algorithm to cover some basic case for proximity
domain distance handling. In the same time, the local variable
usage of fill_pds() is optimized.
TEST=Build and boot on intel/archercity CRB
ACPI SRAT, SLIT and DMAR (Remapping Hardware Static Affinity) are
generated correctly for 2S system.
Change-Id: I2b666dc2a140d1bb1fdff9bc7b835d5cf5b4bbc5
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81442
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new Kconfig to enable PD controller to PMC mux
configuration. Selecting this config enables direct communication from
PDC to PMC. TCSS_HAS_USBC_OPS enables USB-C operations via the EC. When
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION is selected, disable
TCSS_HAS_USBC_OPS to avoid sending PMC commands from AP/EC.
BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.
Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: Ieeb503393418cdad43384be39ac49c93ba91e4db
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82077
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current fast_spi code uses memcpy for rw. The SPI flash read/write
has 4 byte limit, due to which the current 64 bit memcpy doesn't work.
Hence update rw ops to use read32p/write32p.
BUG=b:242829490
TEST=Verified MRC cache working on MTL 64-bit, future 64 bit platforms
and RPL(brox/skolas) 32-bit platforms.
Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Integrated Boot Logic (IBL) codes doesn't support bootloader
controlled Primary-to-Sideband Bridge (P2SB) hidden and unhidden.
Hence, dynamically read IBL HPET/IOAPIC Bus:Device.Function (BDF)
by bootloader is not supported, because when P2SB is hidden the
register access is denied.
TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB
Change-Id: I3975cb00e215c4984c63bb8510e8aef7d4cc85a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Clean up by using is_devfn_enabled().
Change-Id: I9ea3d8b1b18e84a75a81a7e926d2c638766bb493
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82120
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up by using is_devfn_enabled().
Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In NUMA architecture, all devices (cpu, memory and PCI device)
belong to specific proximity domain. Add utils to map device
instance to their proximity domain.
Proximity domain ID is the index assigned at the creation of
proximity domains. There is no hard relationship between proximity
domain ID and the device identities (e.g. socket ID). Hence we
need the map utils to explicitly link them.
For now the Sub-NUMA config isn't taken into account.
TEST=Build and boot on intel/archercity CRB
Change-Id: Icd14a98823491ccfc38473e44a26dddfbbcaa7c0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81440
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.
Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.
However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.
Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.
Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found in a Clevo V560TU with Intel Core Ultra 155H
Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This patch introduces fsp print helper macros to print
`efi_return_status_t' with the appropriate format. These macros
are now used for fsp debug prints with return status
efi_return_status_t is defined as UINT64 or UNIT32 based on the
selected architecture
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: If6342c4d40c76b702351070e424797c21138a4a9
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the input device pointer pointing to a domain device,
dev_get_domain returns the input device itself.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3a278a8f573de95406ee256fba17767def4ad75d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In coreboot, domain indicates hardware units that provide/group
resource windows, For Xeon-SP, domains are PCIe compatible and
further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX.
Rename dev_get_pci_domain to dev_get_domain to align with coreboot
concept and distinguish from Xeon-SP concept.
TEST=Build and boot on intel/archercity CRB
Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Allows to use the function in more places that expect the
struct device to be readonly.
TEST=Build and boot on intel/archercity CRB
Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81275
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.
Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81637
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Lynxpoint has them, so add them on Broadwell as well.
Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.
Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For current generation SPR/EMR you need to add at least
3 different microcodes having about 2MiB of size in total.
This doesn't work with the hardcoded offset and size in Kconfig.
Since it's loaded through FIT there's no need to pass it to FSP-T.
Drop the hardcoded locations and place it somewhere in CBFS.
Test: Booted on ibm/sbp1 with microcode confirmed loaded in
bootblock on BSP. All the APs also have the correct
microcode version loaded.
TEST= Build and boot on intel/archercity CRB
'cat /proc/cpuinfo | grep microcode' result doesn't change
before and after this patch.
Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Compress FSP-S to save some space in CBFS.
Reduces the size of debug FSP-S by about 25%.
Test: Still boots on ibm/sbp1.
TEST= Build and boot on intel/archercity CRB.
Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Integer division in C truncates toward zero. When the dividend and the
divisor are positive, one can add half of the divisor to the dividend to
round the division result towards the closest integer. We already have a
macro in commonlib to do just that, so put it to good use.
Tested with BUILD_TIMELESS=1, coreboot images for the Asus P8Z77-V LX2
and the Asrock B85M Pro4 do not change.
Change-Id: I251af82da15049a3a2aa6ea712ae8c9fe859caf6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52651
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<device/pci.h> is supposed to provide <device/pci_{def,type}.h>
Change-Id: Ia645b8dba8c688187a25916f508593f333821f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.
Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Avoid calling `acpi_device_scope()` and `fast_spi_acpi_hid()` if the
result won't be used. Also, reorder a condition so that compile-time
constants appear first, so as to help the compiler optimize it out.
Change-Id: I42ce55c2978ad9c593c359c5decd5842fb3a97a1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.
After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.
TEST=Build and boot on intel/archercity CRB
Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
