This is going to be used by some devices, map the next available
extended code to it.
Change-Id: Ib4fc6c33e10f273a73f3a6ca40deeefa3ab70f20
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90617
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Depending on the Kconfig, LAPIC may be in either xAPIC or x2APIC mode.
However, coreboot generates MADT LAPIC entries based on APIC ID rather
than currently enabled LAPIC mode. This resulted in LAPICs enabled in
x2APIC mode being described as xAPICs in MADT.
Create appropriate MADT LAPIC entries based on currently enabled mode
by calling is_x2apic_mode.
TEST=MADT describes LAPICs in x2APIC mode on Gigabyte MZ33-AR1, matching
the actually enabled LAPIC mode.
Change-Id: Iebbbca415f0b775339cbfab5c24848940d92878d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89475
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Running FWTS detected a problem with FACS having non-zero
values in reserved fields:
FAILED [MEDIUM] FACSReservedNonZero: Test 1, FACS Reserved field must be zero,
got 0x00fe7bcd instead
FAILED [HIGH] FACSReservedBitsNonZero: Test 1, FACS OSPM Flags Bits [31..1] must
be zero, got 0xf23bcdd8 instead
FAILED [LOW] FACSInvalidReserved1: Test 1, FACS: 2nd Reserved field is non-zero
Clear whole FACS table and then start filling the non-zero values to
fix the issue.
TEST=Run FWTS V25.01.00 on Gigabyte MZ33-AR1 and see no error for FACS
test.
Change-Id: I2af4caea155e3707e3b7832824e81e6b69f836a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is going to be used in some devices in place of KEY_ASSISTANT, map
it.
BUG=b:446676921
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I006c232c2924e8b6dc06338b0282c76f1f529a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90026
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like some devices may be using the capslock key, this a standard
code, just map it.
BUG=b:446677367
TEST=flashed and tested on a brox board, checked that the correct code
is generated with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Ieb0f55e7f25a1b34d226efe12ad9dc481a53a082
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90025
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Chromium OS EC has some specialized handling of chromebook specific
function keys on the keyboard top row, these have a function specific
action key code that is exposed to the OS and used to map their
position, and also a specific scancode that has to be mapped to a Linux
event code.
This adds the necessary mapping for KEY_HOMEPAGE, which is going to be
used in new devices.
The scancode picked is 0xe012, which maps to e02a or 0xaa, the
corresponding EC CL is:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/7118961
BUG=b:446007724
TEST=flashed and tested on a brox board with chromiumos, checked the
code with evtest
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I395721a342f507453dae19373df2f189ac1b5dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90024
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This moves most of the vendor and architecture independent code into
common ACPI code.
Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
smbios_mainboard_enclosure_type() is not linked when SMBIOS
is disabled. Fixes a linker error when the user disabled SMBIOS
table generation in Kconfig.
Change-Id: Ic3e70c658d01a839eb37f0862f31ee9f65a84300
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89280
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support runtime evaluation of the TPM base address
introduce and use a new method for CRB TPMs.
Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.
We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.
Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
This reverts commit 6b446b991b.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, the 'acpigen_write_byte_buffer' function required both the
byte buffer length and the initialization data byte array 'arr'. The
ACPI spec however allows buffer declarations with only the length, but
without an initialization data byte array. In this case the AML
interpreter will create a buffer of the given length with all bytes
initialized to 0x00. In order to not need another function, allow the
'arr' parameter for the pointer to the initialization data byte array to
be NULL and in that case don't write the optional buffer initialization
byte array.
TEST=Calling 'acpigen_write_byte_buffer' with 'NULL' as first parameter
results in the AML code sequence being written which decompiles to ASL
as expected.
Change-Id: Ie756489e02f994c38d38907a97fb215d30f4a636
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86631
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement functions to write the AML bytes corresponding to
CreateBitField for both OP buffers and named buffers.
TEST=Calling 'acpigen_write_create_buffer_bit_field' results in the AML
code sequence being written which decompiles to ASL as expected.
Change-Id: Ia5c06c2e8564b64de386871b2faf79c433e5a1da
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement functions to write the AML bytes corresponding to
'If (LNotEqual (...))' which is equivalent to 'If (LNot (LEqual (...)))'
for the value types combinations 2 OPs, OP and value, and namestring and
value.
TEST=Calling 'acpigen_write_if_lnotequal_op_int' results in the AML code
sequence being written which decompiles to ASL as expected.
Change-Id: I6c664bc4d30a49ae990eeb9f0e0776cac37efc57
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If CONFIG(CRB_TPM) is enabled but the TPM is inactive, and no other TPM
interface (SPI, I2C, Memory-Mapped) is configured, the function would
incorrectly fallback to generate a TPM2 table for FIFO mode.
This commit adds a check to ensure crb_tpm_is_active() is only
called if CONFIG(CRB_TPM) is enabled and no other TPM interface
is present. If the CRB TPM is inactive and no other TPMs are
available, the function now exits early to prevent generating
an invalid TPM2 table.
Test=boot `starlabs/starlite_adl` and check Linux doesn't probe for a
TPM when PTT is not active.
Change-Id: I153779aa1f3d84ffeb694543f9da1d09b120f98f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Some upcoming patches run up against the existing limit, which
was added 16 years ago without any justification as to the size.
Bump the size from 10 to 15, to prevent tripping the runtime assertion.
TEST=Tested with rest of patch train
Change-Id: I8362b3a63a23bea0ce47920e5d41cd2535dbc084
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Otherwise flags field is pre-filled with random garbage.
Change-Id: Ie5dc0720183b8ba07561341003f28a86ffce911e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Commit ce10b6f821 unhid the BOOT0000
device from Windows. It requires a driver that's available from Coolstars EC bundle.
Guard this against the ChromeEC, so that non-Chromebooks don't get an
error device in Device Manager.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The following functions are added:
_create_buffer_field
acpigen_write_create_buffer_byte_field
acpigen_write_create_buffer_word_field
acpigen_write_create_buffer_dword_field
acpigen_write_create_buffer_qword_field
These functions are to generate:
CreateByteField (<namestring> , offset, <field name>)
CreateWordField (<namestring> , offset, <field name>)
CreateDWordField (<namestring> , offset, <field name>)
CreateQWordField (<namestring> , offset, <field name>)
NOTE:
There are set of acpigen_write_create_[byte/word/dword/qword]_field
functions already, but the field can only be created from Arg[n] or
Local[n] variable objects. A Name object must be first assigned to such
variable. The new functions here will allow us to create field directly
from Name object.
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85197
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add helper function to allow platform to fill gicc parameters for use in
ACPI table.
Change-Id: Ibd4c52a5482707fae8aa1b8b21fdc6bb5f4b45c2
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79973
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IORT table represents IO topology of an Arm based system for use
with the Advanced Configuration and Power Interface (ACPI)
Add helper functions for ACPI IORT table for:
1. ITS (Interrupt Translation Service)
2. SMMUV3
3. ID MAP
4. Named Component
5. Root Complex
Based on document: DEN0049E_IO_Remapping_Table_E.e
Change-Id: I7feaf306b5eea21bfc9a2e2a1a2c3ddc3c683c0b
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79404
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch move keymap size calculation inside of
has_alpha_num_punct_keys condition. When the condition is not met,
it can prevent total keymaps size calculate incorrectly.
BUG=none
TEST=emerge coreboot pass
Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch supports keyboards that have delete key but without
numpad.
To prevent KEY_DELETE be defined twice, move it from
numeric_keypad_keymaps to rest_of_keymaps.
BUG=b:345231373
TEST=Build and test on Riven/Craaskino, delete key function
works
Change-Id: Ib922a2b52fa7152ba3d9deb44e2c8200b2a3802c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83684
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
No need to open-code this when we have a function for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae570ba750cb29456436349b4263808e2e410e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83643
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD
sizes larger than 4KB. If the value in the field is N, the size of
the register set is 2^N 4 KB pages.
Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying
to use the beyond 4KB part of the DRHD BAR if they exist. They need
the DRHD size field to set up page mapping before access those
registers.
Re-add acpi_create_dmar_drhd with a size parameter to support the
needs.
TEST=Build and boot on intel/archercity CRB
Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For most of SoCs, DRHD is by default with the size of 4KB. However,
larger sizes are allowed as well. Rename acpi_create_dmar_drhd to
acpi_create_dmar_drhd_4k to support the default case while a later
patch will re-add acpi_create_dmar_drhd with a size parameter.
TEST=intel/archercity CRB
Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since Qemu doesn't provide an XSDT, coreboot adds one as separate ACPI
table. Qemu only provides the smaller ACPI 1.0 RSDP, but the XSDT can
only fit into the bigger ACPI 2.0 RSDP. Currently the exsting RSDP is
being reused, without a size check, which works fine on the first boot.
However after reboot the XSDT pointer seems to be valid, even though the
checksum isn't. Since the XSDT then isn't reserved again on reboot, the
memory it's pointing to is reused by other tables, causing the
payload/OS to see an invalid XSDT.
Instead of corrupting the smaller existing RSDP, allocate a new RSDP
structure and properly fill it with both, existing RSDT and XSDT.
In addition return the correct length of allocated ACPI tables to the
calling code. It was ommiting the size of the allocated XSDT and SSDT.
TEST: Run "qemu-system-x86_64 -M q35" and reboot the virtual machine.
With this patch applied XSDT is always valid from the OS
point of view.
Change-Id: Ie4972230c3654714f3dcbaab46a3f70152e75163
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83116
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit simply adds support for a Do Not Disturb key. HUTRR94 added
support for a new usage titled "System Do Not Disturb" which toggles a
system-wide Do Not Disturb setting.
BUG=b:342467600
TEST=Build and flash a board that generates a scancode for a Do Not
Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux
kernel with patches[0] that add this new event code using `evtest`.
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb
Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
Add support for an Accessibility key. HUTRR116 added support for a new
usage titled "System Accessibility Binding" which toggles a
system-wide bound accessibility UI or command.
BUG=b:333095388
TEST=Build and flash a board that contains an accessibility key. Verify
that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0]
that add this new event code using `evtest`.
```
Testing ... (interrupt to exit)
Event: time 1718924048.882841, -------------- SYN_REPORT ------------
Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1
Event: time 1718924054.062428, -------------- SYN_REPORT ------------
Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9
Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0
Event: time 1718924054.195904, -------------- SYN_REPORT ------------
```
[0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a
Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Forest Mittelberg <bmbm@google.com>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both acpi_create_madt_sci_override and acpi_sci_int have special
handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly
obvious, so add a comment with the reason for that.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82643
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call acpi_create_madt_irqoverride from acpi_create_madt_sci_override
with the correct parameters instead or re-implementing the same
functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e6ee0eed837c2d46da62092b7cc5669dc177d8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82644
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Both the processor local APIC structure and the processor local x2APIC
structure use the same flag bit definitions. ACPI spec 6.4 was used as a
reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The multiple APIC flags table from the ACPI specification version 6.4
was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82640
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For PCI domains, static _OSC will be used for better readability
and maintenance.
This reverts commit f4a12e1d39.
TEST=Build and boot on intel/archercity CRB
Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix ++ as suffix and * precedence. After modification, the gpio index
can be obtained correctly.
The error was introduced in the commit making it public:
commit 01344bce
BUG=None
TEST= Can get the correct index test on nissa.
Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82088
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding. This
commit simply does so by examining the keyboard capabilities reported by
the EC.
BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.
Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Some devices may generate scancodes for the Fn key if they have one.
If they do, we should add them to the linux,keymap binding.
BUG=b:333096023
TEST=Flash DUT that emits a scancode for the Fn key, verify that it is
mapped to KEY_FN in the Linux kernel using `evtest` when pressing the Fn
key.
Change-Id: Ie4daa64bc6b619392276d0b5f16e2d195d5bd68c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Make sure it can be used for other driver.
At present, i2c_generic_write_gpio() is not suitable for being called
by other drivers, so delete it, add acpi_device_write_dsd_gpio() to
replace it, and make it public.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This prevents name clashes with drivers/spi/tpm and allows both to be
potentially compiled in at the same time.
Change-Id: I0aa2686103546e0696ab8dcf77e2b99bf9734915
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some internal keyboards have a dictation key; this commit simply adds
support for this key by adding the mapping from the scancode to the
Linux keycode for use in the linux,physmap ACPI table.
BUG=b:333101631
TEST=Flash DUT that emits a scancode for a dictation key, verify that it
is mapped to KEY_DICTATE in the Linux kernel.
Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
<device/device.h> is supposed to provide <device/{path,resource}.h>
Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add dynamic PCI domain _OSC ASL generation codes, supporting both
PCIe and CXL domains.
Dynamic SSDT generation is used to generate a list of ASL device
objects based on FSP outputs (e.g. the SoC/SKU configurations)
and _OSC is a method inside these objects (hence it would be
straightforward to be generated altogether, plus some C codes
managed boot configs could be referenced as well).
This usage is optional. It is helpful for cases where the same
code set supports multiple SKUs/SoCs (difficult to be handled by
one set of static SSDT), and the CPU performance is good enough
to run SSDT generation logics with minimal costs.
TEST=intel/archercity CRB
Tested with https://review.coreboot.org/c/coreboot/+/81377.
Change-Id: I711ce5350d718e47feb2912555108801ad7f918d
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2
during compilation, in which case actual TPM family in use can be
determined at runtime.
In some places both compile-time and runtime checks are necessary.
Yet in places like probe functions runtime state checks don't make sense
as runtime state is defined by results of probing.
Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print bus number, IO and MMIO ranges as fixed length zero-padded
hexadecimal numbers. The bus numbers are 1 byte long, the IO range
values are 2 bytes long and the MMIO range values can be up to 8 bytes
long, so use '%02x', '%04llx' and '%016llx' in the corresponding parts
of the format string.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
