The MCA MSRs aren't getting cleared and no microcode update gets applied
for now. Both will be added later.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SerialIO is in ACPI mode for google/auron and intel/wtm2, and is
disabled for google/jecht and purism/librem_bdw. Since Broadwell
SerialIO is never used in PCI mode, _ADR can safely be dropped.
Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also aligns Stoneyridge with Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup the config required to support verstage.
The offsets are the same as picasso.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Required so we pass SPI information down to depthcharge.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is a copy/paste of amdblocks/lpc.h. The registers are different for
picasso and cezanne, so I'm moving them to soc.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4dfadcdc025d3581cb1423e9793a9b2181742b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
PEP table is applicable to Skylake platform as well. It is required to
make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix
hooks.
Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U),
intel_pmc_core kernel module is loaded and reports statuses predictably
via debugfs.
Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The transfer buffer is only required when using
VBOOT_STARTS_BEFORE_BOOTBLOCK.
The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK
or VBOOT_STARTS_IN_BOOTBLOCK.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
southbridge.c was renamed and split into early_fch.c and fch.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the PSP didn't like a command this should be at least a warning on
the console and not just a debug message.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reduces the differences between Lynx Point and Broadwell.
Change-Id: Ib53d73e3f89c538ba0f052a98c7aabe815a59472
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SCI IRQ is always set to IRQ 9 in the bootblock. To allow using
common MADT code on Broadwell, hardcode it as 9 everywhere.
Change-Id: I84345b7985b1996369cecc4bcb0a3668d002a922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):
1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH
In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.
BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.
Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 75f6ab35ff.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a copy/paste of picasso with a few things removed. With this
change we can jump into depthcharge.
Allocated resources:
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
PCI: 00:00.0 resource base 2000000 size 1c0000 align 0 gran 0 limit 0 flags f0004200 index 4
PCI: 00:00.0 resource base 21c0000 size cde40000 align 0 gran 0 limit 0 flags e0004200 index 5
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:00.0 resource base 100000000 size 30e340000 align 0 gran 0 limit 0 flags e0004200 index 6
PCI: 00:00.0 resource base 40e340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 7
PCI: 00:00.0 resource base 40f000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 8
PCI: 00:00.0 resource base 410000000 size 20000000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base cfffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index a
PCI: 00:00.0 resource base ceffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
TEST=Boot majolica and see depthcharge finally loading:
Starting depthcharge on MAJOLICA...
new_rt5682_codec: chip = 0x1A
Looking for NVMe Controller 0x3004cac8 @ 00:01:07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I52682ec2a06c7e219c221648f241e18e26a9358e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50339
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
