No board defines this macro. In preparation to drop OptionsIds.h files
from mainboards, remove commented-out references to `IDS_DEBUG_PORT`.
Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The values were copied from Foxconn D41S, which uses a different codec.
Adjust the codec config as per the settings dumped from vendor firmware.
Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable Display Controller Engine Audio endpoint to enable HDMI audio.
BUG=b:186479763
TEST=Build and boot to OS in guybrush.
Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Everybody wants a stylish stylus. Enable the power system to it.
BUG=b:186267293
TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC!
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common
folder and rename to rtc_mt6359p.c.
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I73ea90512228a659657f2019249e7142c673e68e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PIC IRQs are required so we can correctly set up the PCI_INT
registers. This only matters when booting in PIC mode. We don't need to
set the IO-APIC registers since the linux kernel will auto-assign those
to reduce conflicts.
BUG=b:184766519
TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and
verify xhci and graphics continue to work.
$ cat /proc/interrupts
12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci
13: 100000 XT-PIC xhci-hcd:usb1
14: 4032 XT-PIC amdgpu, xhci-hcd:usb3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mcache is overflowed in the latest build. In order
to fix the mcache overflow, we increase the mcache size
to 0x4000 and adjust the percentage to 50% for the ro/rw
mcache. This change is for all of the volteer variants
as we see many of the volteer variants which use the
latest bios having the mcache overflow issue.
BUG=b:187095474, b:187095765, b:187234881, b:162052593
TEST=no mcache overflow in the bios log
Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add backlight support in sn65dsi86bridge through the AUX channel using
eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board.
Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace `3` with `SaGv_Enabled`, which has the same value.
Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Create the volet variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:186334008
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLET
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Bank interleaving does not work on this platform, disable it.
AmdInitPost returns success thanks to this setting.
TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to elemi for K4AAG165WB-BCWE
BUG=b:187379245
TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage
Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for
the LPDDR4 version. This changes to use SODIMMS.
Further changes may be needed for platform customization, so I put the
config file in variants/baseboard instead of the root mancomb directory.
BUG=b:187094481
TEST=Build only
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not
used for the reset.
DRIVERS_UART_ACPI - Add the UART ACPI code
FW_CONFIG - Mancomb uses the firmware config interface
PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly
to send post codes to the EC, so disable them for now.
BUG=None
Test=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
This same patch was added for Guybrush at CB:52673
BUG=b:186045622, b:181139095
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.
BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SPI flash is not emulated on these boards.
Change-Id: If29a87441cb26e53c9814ed10ddcfe14752c3965
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52791
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
BUG=b:186380809
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.
BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the pirika variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:184157747
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_PIRIKA
Signed-off-by: kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52626
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pen Detect GPIO is exported through GPIO keys driver to the kernel so
that stylus tools is popped on pen eject event. Hence enable the GPIO
keys driver and configure the devicetree.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is
added to the ACPI SSDT table. Ensure that the Pen Eject events are
detected.
Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1620159356.243180, -------------- SYN_REPORT ------------
Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Ensure that when the device is suspended, it wake on Pen Eject event and
does not wake on Pen Insert event.
Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=Wake system from S0i3 with EC and see GPE 3 increment.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS on shadowmountain. Ensure that the
EC Software Sync is complete.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device.
BUG=b:186070097
BRANCH=puff
TEST=Build and make sure TS works to wakeup suspend/resume.
Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only 4 mainboards selected to use the option table.
Use the same default on all boards.
Change-Id: Ia9ef88d5158a2b43f843c26b5b366a899dad8788
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz
BUG=b:179170193
BRANCH=firmware-zork-13434.B
TEST=verified that the resolution of the display is 4K 30Hz
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
