Found on tiny firewall appliance from Chinese company named "Topton"
with Intel N100 SoC. This system is fanless so all we need is the
ability to use serial output (RS232 in RJ45 form-factor, called
"Cisco-style" at address 0x3f8), which is working.
Change-Id: I9c27f52785d294a6f7c315b8df47d4dd5b389414
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84176
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This properly supports power_on_after_fail setting on affected
mainboards.
Tested on GA-H61M-S2PV
Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since a generic ITE GPIO driver is available and in use, the existence
of chips-specific drivers no longer make sense. Remove the dead code
in favor of generic GPIO driver.
Change-Id: I7e031d12192af4bd47923d87c1d02c64f9c851a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83497
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the driver for ITE SIOs supporting the GPIO register layout
(confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs
with unavailable datasheets are unmodified).
Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM
and must then provide the number of GPIO sets specific to a chip
via SUPERIO_ITE_COMMON_NUM_GPIO_SETS.
Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a generic driver to configure GPIOs and LEDs on common ITE
SuperIOs. The driver supports most ITE SuperIOs, except Embedded
Controllers. The driver allows configuring every GPIO property
with pin granularity.
Verified against datasheets of all ITE SIOs currently supported by
coreboot, except IT8721F (assumed to be the same as IT8720F),
IT8623E and IT8629E.
Change-Id: If610d2809b56c63444c3406c26fad412c94136a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2
(For H Version)".
TEST=Initialize IT8659E on the new Protectli platform
Change-Id: I11657ec6e1c880f0cee247071486a904a92bb7a1
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Introduce HAVE_SHARED_PS2_PORT Kconfig for this Super I/O to have
mainboards indicate if they have one shared PS/2 port on the rear
panel. On these boards (where a Y-cable cannot allow both
keyboard and mouse to work off the same port), if a PS/2 keyboard is
not present, SIO should be configured to swap its role to mouse, to
allow the OS to find and initialize any mouse connected.
Supporting code will come in a separate patch. Idea is to condition
them on this Kconfig.
Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82631
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.
Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A function to disable the PME# output was added. This is required to
set up the SuperIO on the "HP Pro 3500 Series" mb.
Change-Id: I94f023ba6eb24b5fb1c5e0b30eb65738f50a87eb
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81589
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.
Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A number of ITE SIOs support "special fan control vectors", which
effectively allow non-linear fan speed control. This is for example used
by the vendor firmware of the "HP Pro 3500 Series".
The special vector registers won't be written to until the mb's
devicetree configures `FAN_VECX.tmp_start != 0`.
Change-Id: I93df2b5652fc3fde775b6161fa5bebc4a34d5e94
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The it8772f is now configured by the much better common code that is
used for other chips in the family as well. This mainly concerns the EC,
the GPIO functionality was not moved to common as it currently lacks a
sane abstraction in any codebase.
The datasheets of the it8772e(f) and it8728f (for reference) were
studied and verified against the common code, adding exceptions where
needed.
Change-Id: Ic4d9d5460628e444dc20f620179b39c90dbc28c6
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81310
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add Kconfig option for full-speed setting. Some variants do not support
the full-speed at limit configuration (IT8772F). Keep it enabled for all
current variants that use the common EC code as it was previously
enabled unconditionally - datasheets weren't revisited individually.
Change-Id: Icf24ea1c4f41771a18803957456f0aeba0e51b13
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81525
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix warning for disabled thermal inputs.
Fix warning for PECI thermal inputs if one was set up previously.
Depending on the mb, the superio will not go through power-on reset and
retain its registers. Do not trigger a warning if the current register
value aligns with the desired value. Don't return early if some input is
already configured for PECI, simply overwrite the configuration.
Both warnings were observed while porting the "HP Pro 3500 Series" mb.
Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs
are an example where the LDN is always active. The pnp_generic.asl can
be used to describe the GPIO LDN resources configured by the platform,
however the register 0x30 is always 0 for these LDNs, so OS will not
claim the reported resource for the GPIO device, because _STA will
return inactive LDN.
Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an
always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS
for SIOs which use the pnp_generic.asl preserving the previous states,
except the ITE GPIO LDNs.
Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This renames bus to upstream and link_list to downstream.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Macros can be confusing on their own; hiding commas make things worse.
This can sometimes be downright misleading. A "good" example would be
the code in soc/intel/xeon_sp/spr/chip.c:
CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev,
This appears as CHIP_NAME() being some struct when in fact these are
defining 2 separate members of the same struct.
It was decided to remove this macro altogether, as it does not do
anything special and incurs a maintenance burden.
Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I41191f6971bdd8ecff2c56f4bfa2b57c87530b83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80076
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
In commit 0a0945c6a2 (sio/nuvoton/npcd378: Use acpi_device_path_join),
some oversights were made. Instances of "strconcat(scope, ..." should be
replaced with "..._join(dev->bus->dev, ..." instead of "..._join(dev, ...".
On HP 8200 USDT, this fixes ACPI error like this on resume from S3:
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.LPCB.SIO0.L040.RMFG], AE_NOT_FOUND (20230628/psargs-330)
ACPI Error: Aborting method \_GPE._L08 due to previous error (AE_NOT_FOUND) (20230628/psparse-529)
ACPI Error: AE_NOT_FOUND, while evaluating GPE method [_L08] (20230628/evgpe-511)
RMFG seems to be a typo of PMFG made in that same commit.
Change-Id: Ifffa7ad72cfdb644c8b5147132a5fd56511ed33b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Used by the OptiPlex 3020/7020/9020:
- EMI and Runtime registers work
- UART1 works (including IRQs)
- PS/2 keyboard and mouse untested
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I9323198f1139cd0c3dd37f977ae7693b721654f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This achieves the same without the strconcat & free dance.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4d8e9bae6085a6e05847b01497fb4b51041ca7b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SCI handler for the GPE associated with the Super I/O did not clear
the respective PME status bits resulting in the SCI reoccurring
endlessly. The /proc/interrupts reported millions of ACPI interrupts
generated in just a few minutes of uptime. The flood of interrupts
caused some units to be unusable in extreme cases once attempted to
boot Qubes OS for example. On systems like Qubes OS it had a huge
impact on performance due to many IPCs the SCIs caused under Xen.
Clear the PME bits of devices that report a PME event. Then clear
the global PME status bit at the end of SCI handler to prevent the SCI
from asserting again until a new event occurrs. With this change
the number of ACPI interrupts generated in the first minutes of uptime
settles at a few thousands.
TEST=Boot Qubes OS R4.1.2 on Dell OptiPlex 9010 SFF and check
/proc/interrupts in dom0 if the number of ACPI interrupts is only
a few thousands.
Change-Id: I64e03d268138a62b46084be41343ef7fb089dfc3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Due to copy-paste error, the UART2 device name is the same as
UART1. Fix it.
Change-Id: I796d09f321101a36731a56099af738c9485df8a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2df260cea6f12f5a3a6cbae3c7b99bab244a556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The fixed I/O resource descriptor macro implies that the device will
only decode 10 of the 16 IO port bits causing aliasing. Use an I/O port
descriptor instead and use Decode16 to tell the OS that this I/O
resource will decode all I/O address bits.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6183d625fb7968fb33caf396f19feef8917ba4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Since it was the only super I/O in the serverengines folder, also drop
the parent folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I610c94bc100c9d5558da442b2847d8f26de07820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77064
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
The patch creates a chip directory for IT8784E used by
protectli/vault_cml platforms.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The SuperIO ACPI name was hard-coded to "SIO0". Allow setting the name
in the device tree so more than one SuperIO can be named.
An upcoming board (purism/librem_l1um_v2) has two SuperIOs - one in the
AST2500 BMC, and a Nuvoton NCT6791D used for hardware monitor, POST
display, etc.
Many boards have references to SIO0 already, so the default name is
still the same for a single SuperIO.
Change-Id: Ibfa6ab7622749e6310ee91530bc3722e8e28d9bb
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.
TEST=build/boot Win11 on samsung/lumpy, verify keyboard functional.
Change-Id: I7b6b09da1a3fdc34ef43789c699f7fd22b4b655b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace Divide (a,b,c,d) with:
c = a % b
d = a / b
Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
