The same GPIOs are used on both platforms, definitions are added an a
new .h to make it easier to re-use them across the code.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=panel backlight still enabled on Gru as before. The rest of the
GPIOs are used in the upcoming patches.
Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: c587880
Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346219
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15029
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable virtual dev switch config.
BUG=None
TEST= On Dev FW screen, press SPACE key to boot to normal mode
Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/15080
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add ADI vendor
Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes,
only string and ifdef names changed.
Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/14778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
thermal.h still has references to X230 in include guard since it
seems to have been copied from that port. Code formatting changes
in romstage.c.
Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56
signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/15071
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since the sd card cmd, data, cd lines are configured
as native mode, allow the native controller to control
the termination.
Configure SDCARD_CLK_FB which is used for calibrating the
timing of the actual clock buffer.
BUG==chrome-os-partner:53747
TEST=verify sd card detection
Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15096
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
This creates a config for the x60 audio based
on values taken from vendor bios.
The pin config is stored in (for linux 4.5 at least):
/sys/class/sound/card0/hw*/init_pin_configs
In the left column there is the pin number.
In the right column there is the default configuration of that pin.
(This has to be done while running the proprietary bios)
More information on the sound card can be found in:
/proc/asound/card0/codec#*
This also hold the information of /sys/class/sound/
What is improved:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker
Before this had to be done manually in alsa or pulseaudio.
TEST= check if internal microphone is used by default in
pavucontrol if you are using pulseaudio.
Plug in a jack with headphones and check if there
is sound output through these and not the build-in
speaker.
Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15063
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14987
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds asl code to include support for Google ChromeEC.
We need this to show the battery icon and notifications like charger
connect/disconnect etc.
BUG = 53096
TEST = Plug/Unplug AC Adapter multiple times and make sure the battery
connected is charging properly.
Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15069
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Update the DDR config and DRAM driver to allow running at up to
928MHz. Kevin config/clock rate are not being changed, but Gru now
runs at 928 MHz.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru,
Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9
Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/343984
Original-Reviewed-by: Stephen Barber <smbarber@chromium.org>
Reviewed-on: https://review.coreboot.org/15027
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Just the memory size, there is no strap to identify PCB revision.
Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14997
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The way dispatcher table is set up prevents linker from
optimizing unused code away, we currently have raminit in ramstage.
Optimize this manually by configuring AGESA_ENTRY booleans for
romstage and ramstage separately. This will remove references in
FuncParamsInfo and DispatchTable -arrays.
All boards now include multi-core dispatcher, it has minimal footprint:
AGESA_ENTRY_LATE_RUN_AP_TASK
ACPI S3 support depends on HAVE_ACPI_RESUME being enabled:
AGESA_ENTRY_INIT_RESUME
AGESA_ENTRY_INIT_LATE_RESTORE
AGESA_ENTRY_INIT_S3SAVE
Disabled for all boards as it was not used:
AGESA_ENTRY_INIT_GENERAL_SERVICES
Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14417
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Setting the size of the preallocated memory for the igd is done
using a cmos parameter, gfx_uma_size. This was limited to a subset of
all available sizes, that were already implemented elsewhere
in the northbridge code.
What this does is change the cmos parameter to 4 bits instead
of 3 bits to accomodate all vram sizes.
It also adds a sane default of 32mb that already was in place.
The northbridge code that reads this cmos parameter is
also changed for this new cmos settings.
352M is disabled since it causes issues on systems with 4GB or more ram.
TEST: Build, flash target. Clear cmos by corrupting
the checksum (nvramtool -c something).
Set a desired value in gfx_uma_size using nvramtool.
"dmesg | grep stolen" to see what is actually allocated.
Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14900
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Follow-up on commits a5d72a3 and 53052fe for f12 and f15.
OEM Hooks are not BiosCallOuts.
Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14888
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The included file does not declare pm_ioread(), and the
modified file does not call it either.
Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14968
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
See initialize_ecc() for the awful hack that got us around cache-as-ram
being invalidated as we do ECC HW scrubbing. It once worked, but
compiler nowadays puts more registers on the stack.
Not much interest to try fix ECC for this particular board.
Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15014
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC
and Galileo board.
TEST=Build and run on Galileo Gen2.
Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Return the correct board version in SMBIOS.
TEST=Build and run on Galileo Gen2
Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
These files do not use definitions from OptionsIds.h. Also those
definitions are required and already included for Ids.h.
Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU
model and a dGPU model.
Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14632
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
TPM should be only be reset once in verstage.
BUG=chrome-os-partner:51096
TEST=Depthcharge no longer shows TPM error.
BRANCH=None
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3
Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9
Original-Reviewed-on: https://chromium-review.googlesource.com/343537
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14845
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Enable the PEG device in devicetree to expose the
device if any. This is already default behaviour
for T5xx series.
Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Add a universal hybrid graphics driver compatible with
all supported lenovo devices.
Hybrid graphics allows to connect the display panel to
either of one GPUs.
As there are only two GPUs one GPIO needs to be toggled.
In case the discrete GPU is activated the panel is routed to it.
On deactivation the panel is routed to the integrated
GPU.
On lenovo laptops the dGPU is always connected to PEG10 and it is
save to disable the PEG slot on dGPU deactivation.
Use common gpio.c for southbridge I82801IX.
Tested on Lenovo T520 using Nvidia NVS 5200m.
Removed Lenovo T430s from the list of supported devices,
as the T430s only supports "muxless Optimus".
Depends on change id:
Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
I8bd981c4696c174152cf41caefa6c083650d283a
Iaf0c2f941f2625a5547f9cba79da1b173da6f295
I994114734fa931926c34ed04305cddfbeb429b62
Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
This reverts commit 59597ead1f.
Will be replaced by lenovo common hybrid driver.
Change-Id: I994114734fa931926c34ed04305cddfbeb429b62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12895
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
IFWI region holds different components required for booting including
CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add
section for IFWI in chromeos.fmd
Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15000
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The use of HSUART0 on galileo requires early initialization of the I2C
GPIO expanders to direct the RXD and TXD signals to DIGITAL 0 and 1
on the expansion connector.
TEST=None
Change-Id: I11195d79e954c1f6bc91eafe257d7ddc1310b2e7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15010
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Turn on reg_access during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: Iff1616836d6031f43d7741693febefa0bf26b948
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Select HSUART1 for console.
TEST=Build and run on Galileo Gen2
Change-Id: I4425af4dc8b3730b3fa2108d6cc2941bc22c2cdb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15005
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Split out enabling FSP 1.1 support to prepare for enabling FSP 2.0
support.
TEST=Build and run on Galileo Gen2.
Change-Id: Ic4e814bcf61f9480f98e2d7bc7a1648dec43a07d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15001
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-ninja-5216.383.B
commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA]
TEST=built and booted Linux on ninja with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/14950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the website URL to the board info and also enables
the realtek nic reset function as per a previous patch.
Change-Id: I2cda120c59b55f0dd2ffa78d397b16beb13d6843
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14954
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds DMI/EP init to the board and fixes
a couple of minor things.
Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14926
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Previously, due to a bug in devicetree and incorrect IRQ
settings in ACPI, SATA controller would not initialize
any HDDs in the OS, even though it worked in SeaBIOS.
The devicetree setting is not needed because SATA must
function in "plain" mode on this board, as "combined" mode
does not work at all.
Change-Id: I0036c4734de00b84cc3d64f38e4b1fd80fd1a25d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14776
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232
serial port, however it is disabled by default due to the SuperIO
default pin mux settings. Enable the secondary serial port early
in romstage to allow use during / after initial boot.
Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14892
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This matches the change in depthcharge fmap.dts to remove si-all
region and mark si-desc as ifd.
CQ-DEPEND=CL:347986
BUG=chrome-os-partner:53689
BRANCH=None
TEST=Compiles successfully
Change-Id: Ic7ed94fcdfb9a79bd6ceb960830f67678b0291b6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14990
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add APU1 prefix because Kconfig throws errors if we try to
define the same variables as choice-entry for APU2 board.
Change-Id: Ic071600dd88e391a8a278d63aad13abd01fd3c9d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14988
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
An updated descriptor expands the BIOS region while descreasing
the 'device expansion region' utilized by the CSE. Update the
end region marker to reflect this new size as well as the
chromeos.fmd file which needs to be adjusted for logical boot
parition 2 requirement which resides halfway through the BIOS
region. The GBB was moved and shunk to accommodate the change.
Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The chromeos.c suport needs to be linked into verstage so it will
link.
Change-Id: If85e232a3721443edfbbd278b32f72302f13f3a8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14973
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
2. Make 20k Pullup and remove duplicate code.
Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Providing an option to enable or disable ISH interface. Leaving it
disabled for now.
Change-Id: Id4e71d60a6c2da6c6c070d41f66f6c161de38595
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Increase BIOS region size by 512KB since device extension size
is reduced from 1MB to 512KB
BUG=chrome-os-partner:52589
TEST=Build Coreboot and boots
CQ-DEPEND=CL:*259448,CL:345642,CL:*259445
Change-Id: Ib81b117a3afe730aafa54b4ef31b1e9ab1f67111
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14929
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on the USB device port.
TEST=Build and run on Galileo Gen2
Change-Id: Ic1fbb2cd51414ce927f2b408ccd27c7edf978744
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14943
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Elan trackpad needs greater sda hold time.
Configure IC_SDA_HOLD register to increase
the i2c sda hold time by 0.3us.
Change-Id: I3d966eed62a059ecb6a0a88e9f4e6b4ba7a925e4
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Select aclk_emmc and clk_emmc source from GPLL, and both to 198MHz,
that is GPLL(594MHz) divided by 3.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot kevin rev1 to chromeos prompt from both emmc and sdcard
TEST=LoadKernel faster, more than twice as I measured manually.
Change-Id: I2580c43b8c79049c3fe16bbf60bfa1a8e0559948
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 5fd37b66dcce77354e1cafab0d6e806d832c08d2
Original-Change-Id: Id22815b302af3204e0e5537af99c1577b09b0877
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339152
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14855
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
