This is now drawn (indirectly) from main usb_port_config.
Also drop it from autoport.
Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the aliases are used and already contain the device name,
there's reason to generate these in the first place.
TEST=Ran autoport with logs from ASRock Z77 Extreme4.
Change-Id: I3378801f5a997a802da61f2b7c4e820f39064019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85822
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, Add_gpl() was only used with C and ASL source code files,
and was hard coded to use the C /* */ style comment, preventing it from
being used with files with other comment styles. Convert this into a
generic function for adding arbitrary SPDX license identifiers for
arbitrary filetypes. This replaces the hard coded GPL-2.0-or-later
string used in gma-mainboard.ads with a call to the new function.
This is also used to add SPDX headers to Kconfig and Makefile sources;
as previous commits added them to all such files in the tree.
Tested against logs from a Latitude E6430 (Ivy Bridge) and Precision
M6800 (Haswell) to check that license headers that were already being
generated did not change.
Change-Id: I24a1ccd0afb7045e878bf6eaae7a23f828a9240d
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel chipsets from ICH7 through Lynxpoint use the same GPIO register
format and thus mainboards using using these platforms have similar
gpio.c files. Factor out the code to generate gpio.c from bd82x6x.go so
that it other chipsets added to autoport can use it.
This was originally written by Iru Cai in his Haswell autoport patch in
CB:30890; I have simply split out the code to a separate commit as it is
a separate logical change.
TEST=Generated output is identical before and after this patch when run
against logs from a Dell Latitude E6430
Change-Id: If1f506f6ad10144bd6acc42505592426bb7193b7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The generated dsdt.asl and early_init.c files contained 2 consecutive
blank lines, so remove one of them.
Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83186
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The southbridge/intel/bd82x6x/pch.h header was previously used to
configure a few registers in SPIBAR, but these have since been moved to
PCH code and the devicetree, making it unnecessary in mainboard.c
Change-Id: I904c95394b4fea73b4990342e647595b5f10335f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82601
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update autoport for:
1. Commit ee12634872 ("nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree")
2. Commit 94625d2aae ("sb/intel/bd82x6x: Allow actual USBIRx values
for native USB config")
As a side effect of #2 above, no more (broken anyway) FIXME comment
will be written for usb_port_config.
Change-Id: I3b8f44d9de19a7446e2fbcbce1aab6ec6583ebe3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 45e4ab4a66 (mb/*: Update SPD mapping for sandybridge boards)
changed the way in which SPD addresses are set up for SNB/IVB boards,
but autoport was not updated to reflect these changes. Result is:
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" # FIXME: Put proper SPD map here"
The stray quote at the end is irritating, but is hard to get rid of
without substantial refactoring of autoport's guts. But, given that
this is a FIXME comment, anyone using autoport should just drop the
comment after verifying the SPD map, so it's not a big deal.
In addition, update the corresponding section of the README, which
was horrendously out-of-date.
Change-Id: I6ad38f53afc4fafb45be7f086723cc0782a965ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82405
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace 3 unused values in the map with those found during a Ghidra
examination of MRC binary, and on hardwares running vendor firmware
(asus/p8z77-m and HP Z210 CMT Workstation).
The outgoing values were introduced in commit 216ad2170c
("sb/intel/bd82x6x: Add new USB currents") in anticipation for
Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually
abandoned. Since commit xxxxxxxxxxxx, such values can be placed
directly in the port config, so there should be no hurdle should that
effort be resurrected.
Add a few #defines in pch.h to place some inline documentation
on MRC values, but more will be documented in the future when this
mapping is introduced MRC-side.
Finally, update autoport to match.
Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Currently autoport fills in USB current '0' if the detected setting
isn't one of the known settings. This works as 0 is a valid setting
from C point of view, but it's not supported on desktop PCs and on
mobile platform results in the lowest possible USB PHY gain. Thus
this might cause instabilities as the original firmware had stronger
USB drive currents and gain settings.
Add more known USB current fields to the map and generate a FIXME
as comment when the detected current isn't one of the known entries
instead of defaulting to 0.
Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This corrects the word "echi2" to "ehci2".
Change-Id: Id8911de147538f4614627cfca449bad528ab6780
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select
ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>,
removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused
includes), as the generated early_init.c uses pci_write_config16().
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.
Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. Also add some comments.
See also these commits:
* Commit a76cf28 with Change-Id
I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables:
Don't initialize already initialized fields").
* Commit 0c52638 with Change-Id
I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove
thermal.h header").
Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was always defined to the same value, and only used twice.
Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.
Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now, autoport used to create a dummy "romstage.c", then write
romstage code to "early_southbridge.c". While it works, it makes more
sense to write to "romstage.c" instead, as virtually all mainboards do.
Change-Id: If9f9375f9a659e7e685de5f884163813261fa656
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28851
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As seen on ASUS P8Z77-V Pro
Change-Id: I9fce9a35174b5120f67c2345a0807db1b843eb48
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
ff4025c5f "sb/intel/bd82x6x: Reduce function-disable mess"
Removed most of the writes to RCBA(FD) and renamed the function to
mainboard_rcba_config.
Writes to FD are properly handled in ramstage, so no need to do it in
romstage.
Change-Id: I4edb75569ceec2d2f1308755a66d286202ca0ae6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This file is no longer there since ACPI pirq routing is now done in an
automated fashion in SSDT.
Change-Id: I8bafafbf670fe0fc2f20b46b5d8abee722931c6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christoph Pomaska <cp_public@posteo.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The idea behind this not to enforce a license on autogenerated code
but is simply out of convenience in the case one wants to make the
result public (in which case it needs to have these license headers).
Change-Id: I1d6b48762b1249bb0becb178a30e1396bf6978fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19510
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This generates better gpio.c files where structs are initialised as
static to be able to drop some entries since those would be
initialised as 0.
This makes these files less cluttered since only relevant things are
shown:
* GPIO direction, level, invert, blink depend on GPIO mode
* GPIO level is read only on input
* GPIO invert is only valid on input
* only show when GPIO are inverted, blinking, reset by RSMRST#
Change-Id: I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
AFAIR from reviews, writing the PMIR (aka. ETR3) register never turned
out to do anything useful.
Change-Id: I119fb1212f360a59b695e2dfef68e19c330d01ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The AFC—Additional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
In accordance to change I8bd981c4696c174152cf41caefa6c083650d283a
change autoport as well, as suggested by Vladimir.
Change-Id: I7cdaa779c11fd3f791a3ad213c24d927b5da76b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13731
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This is needed for stout EC init.
Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
After commit with Change-Id Ia1839ed3 (sandy/ivy: Include
IRQ routes from platform), update autoport to include
that file into the DSDT.
Change-Id: I14534438d0b433895f384539c8b413eaa53d943a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
