Taeko is going to exchange i2c port for touchscreen and cr50.
BUG=b:211911780
TEST=build pass
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207527331
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Convert EC_GPI_SCI to Kconfig option with default value of
0x50 that is used by most boards.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush.
Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt.
BUG=b:211566312
TEST=emerge-guybrush coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: If449453bc60ed41e104346429babc06a73acef64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Super I/O resources were unused and not listed, causing warnings
during resource allocation. Suppress these warnings by setting them to
zero.
Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41459
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bugzzy uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.
BUG=b:205496327
BRANCH=dedede
TEST=Verified touch screen worked with test coreboot
and test touch screen 028D firmware
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
- Set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I20d79d4b42908314dbf7021a67b92e5fd2b79556
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I72c0e0c3968cb2e92b35381691762148f4c270e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I71f22100fe56a8b88321d220f98ac03887ce6bd7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I9b523ebee2d2af8585736588306ca687dfe16003
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ifcdfd9fff197391ca0da083e7f6151c2dffe3374
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5c437ee2d62415f9048a24ad4a517fc33eec3cf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ic9e001721baa7b7df89204eed03375e872c93e28
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Id1bbe7d68d9eace3f54e9decbd02f8b2b50d6867
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ieb6626aeb2023ac27eac8a515cc0e561607f9f62
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I1cfea0491f707052db2fbcee078e2c27c5a306c5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I677770168caa95d95fd7d32cadc15ffae8455e8c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ibd78e1c42d6184127277c1b5dea66150027444fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
When using the default initial core display clock frequency, Magolor has
a rare stability issue where the startup of Chrome OS in secure mode may
hang. Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommendation avoids this problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for magolor.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PS8640 is used on Krabby board as the eDP bridge IC. Enable PS8640
and configure display in mainboard_init() to support display in
firmware screen.
BUG=b:210806060
TEST=saw firmware display on eDP panel of krabby and kingler.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I314d5407c40429bb7bc50f36fece58e396b27548
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60447
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'Corsola' (MT8186 Chromebooks) family has two reference designs
(Krabby and Kingler) and all real implementations should follow either
one of the two. To prevent confusion, we should remove the 'corsola'
configuration from Kconfig board names.
BUG=b:210806060
TEST=emerge-corsola coreboot
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib354054e358c0783f6221c2e2a1730b5c6ddba33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60515
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To provide power to PS8640, the eDP bridge IC on krabby, add control
of VRF12 and VCN33 to set voltage from MT6366.
TEST=measure 1.2V from VRF12 and 3.3V from VCN33.
BUG=b:210806060
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
More Brya variants like Brask and Gimble have migrated to use Alder Lake
QS SoC which enables eNEM feature by default. Hence, select eNEM for CAR
by default for these variants.
BUG=b:168820083
TEST=Able to build and boot gimble variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie5734606e58410545a5f5421837080680664707f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
