Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock
code as pnp devices.
Fixes USB and serial on the dock, if it is already connected when
computer is powered on. DVI and ethernet worked without this patch.
Hot-plug is yet to be fixed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7508874d9c821e31e2297ee5876a573b9eac990f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9ab5adbde4
Original-Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18054
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/453375
This is required to pass button information from EC to kernel without
using 8042 keyboard driver.
1. Define EC buttons device using GOOG0007 ACPI ID.
2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I30e42c66dec3a639c172df465a98e8bb9c03ebdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4a0a348e4
Original-Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18641
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452371
Currently, when using `iasl` 20140926-32 [Oct 1 2014] from Debian 8
(Jessie/stable), the build of the Lenovo X60 fails due to syntax errors.
ASL 2.0 supports `<<`. For consistency, right now, coreboot still uses
the old syntax. So use `ShiftLeft` instead, which also fixes the build
issue with older ASL compilers.
BUG=none
BRANCH=none
TEST=none
Change-Id: I030413bf10db3d8b2435d1fd55e96c7a9a0c457d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db94213640
Original-Change-Id: Id7e309c31612387da3920cf7d846b358ac2bdc71
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18520
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/450377
thinkpad_acpi expects a SSMS method to turn on/off the mute LED
and a MMTS method to turn on/off the microphone mute LED. With
these methods implemented the driver can correctly sync the LEDs
with the corresponding statuses.
There seems to be two different bits to mute the audio in the
Lenovo H8 EC:
* AMUT, used internally (for example to disable the audio before
entering S3).
* ALMT, controllable by the OS, which also toggles the mute LED
(if present).
Tested on a X220T and on a X201.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6a33511266f67aa2337b83673ea7a990f33df6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 068edc1c52
Original-Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18329
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/449819
On the models that support it (like the X220) the LED pulses, on
the others (like the X201) the LED powers off.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibcb9d2bfe1c1d93d3af828f1eac7438f38ae2d56
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1ffff7dab
Original-Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18325
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449817
thinkpad_acpi expects a MHKG method which returns the current
state of the tablet mode switch shifted left by 3. If such
method is not found, subsequent laptop/tablet mode events are
ignored.
Tested on a X220T.
BUG=none
BRANCH=none
TEST=none
Change-Id: I0f07edd24cb8edef45ae62df7edc06fcc1aeb68c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 47f87bd93f
Original-Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/18328
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449816
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8c622291d18ebe5433d10f839abb76dfbf92fead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77d6ba911
Original-Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18274
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/449815
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.
This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.
This patch changes the logic to deal with these corner cases.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib0ec4d6bd5ecc128485e89449fca8021c58dd272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9b798d7904
Original-Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Original-Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Original-Reviewed-on: https://review.coreboot.org/18349
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446391
Not selecting the Kconfig option `GENERATE_SMBIOS_TABLES` the build
fails with the error below.
```
CC ramstage/ec/lenovo/h8/h8.o
src/ec/lenovo/h8/h8.c:201:2: error: unknown field 'get_smbios_strings' specified in initializer
.get_smbios_strings = h8_smbios_strings,
^
src/ec/lenovo/h8/h8.c:201:2: error: initialization from incompatible pointer type [-Werror]
src/ec/lenovo/h8/h8.c:201:2: error: (near initialization for 'h8_dev_ops.read_resources') [-Werror]
cc1: all warnings being treated as errors
```
So add the appropriate preprocessor guards to fix the build error.
BUG=none
BRANCH=none
TEST=none
Change-Id: I8d29e84c4664871193e0ca6e40ea22554caea1ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a4a452abc
Original-Change-Id: I3baed452d422539a805c628a8c4a6a8c2a809317
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/17770
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://chromium-review.googlesource.com/445154
This fixes an issue on systems where the S3 state in the pm1 control
registers are not cleared when vboot determines recovery mode is
required on an S3 resume. The EC code will reboot the system knowing
that the EC was in RW. However, on subsequent entry into romstage the
S3 path will be taken and fails to recover cbmem -- forcing another
reboot. To work around that, signal to the platform a reboot is
happening and let the platform perform the necessary fix ups to the
register state.
BUG=chrome-os-partner:62627
Change-Id: I2c0bdffb80979954021203c798cf9bce56eca7d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96a4317fa9
Original-Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18295
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439150
Add a new driver GOOG0006 to report tablet switch
to user space.
On glados based convertible, check that with a new kernel driver
(cros_ec_tbmc) that evtest collects tablet switch changes.
BUG=none
BRANCH=none
TEST=none
Change-Id: I40ce1a7d7c2fac768e5bbe7732572107207db36e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 87d5fb89fe
Original-Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb
Original-Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/430951
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://review.coreboot.org/18173
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439306
In some cases, we don't want the Chrome EC firmwares (both EC and PD)
built directly by the coreboot build system or included in images at
all. This is already supported with EC_EXTERNAL_FIRMWARE but it does
implement a binary (build and include) or (neither build nor include)
policy.
Some cases require the ability to separately control whether the EC
and PD firmwares should be built and included by the coreboot build
system, only included from externally-built images or not included
at all.
This introduces config changes implementing that behaviour, renaming
options to make it clear that they are specific to the Chrome EC.
BUG=none
BRANCH=none
TEST=none
CQ-DEPEND=CL:434278
Change-Id: Ie0b9e2063280a2b596a2d43afae855401319a959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ff24803a3
Original-Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4
Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Original-Reviewed-on: https://review.coreboot.org/16033
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/430678
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17783
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905
Reviewed-on: https://chromium-review.googlesource.com/421167
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The EC switches, including the hardware retrain flag, are
cleared when handing off the vboot state in romstage. However,
one may still want to query the state of the hardware retrain
flag. Thus, add a method to get the flag from cbmem.
BUG=chrome-os-partner:60592
BRANCH=reef
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17869
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2
Reviewed-on: https://chromium-review.googlesource.com/421028
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString().
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209
Reviewed-on: https://chromium-review.googlesource.com/420844
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
For spi_setup_slave, instead of making the platform driver return a
pointer to spi_slave structure, pass in a structure pointer that can be
filled in by the driver as required. This removes the need for platform
drivers to maintain a slave structure in data/CAR section.
CQ-DEPEND=CL:417081,CL:417087,CL:417958
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17683
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573
Reviewed-on: https://chromium-review.googlesource.com/417080
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit 967cd9a [ChromeOS: fix Kconfig dependencies] broke keyboard
interrupts on parrot by making SERIRQ_CONTINUOUS_MODE conditional on
CONFIG_CHROMEOS, which it should not be; fix by moving back under main
board specific options config.
Additionally, Windows [8/8.1/10] fails to enumerate the keyboard when
its ACPI entry is located under the SIO device since it is missing an
_HID entry, so add the appropriate value per ACPI spec 5 ch. 9.7
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17017
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ia69e9b326001d2026b15b4ec03c94f7d03c8a700
Reviewed-on: https://chromium-review.googlesource.com/415081
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Normally firmware should have no business messing with the USB PD role
(source/sink/whatever) in the EC. But, as so often happens, ugly issues
crop up that require weird work-arounds, and before you know it you need
to do this for some reason that only makes sense in context. I do now,
so add this function to send the necessary host command in the simplest
possible fashion.
BRANCH=gru
BUG=chrome-os-partner:59346
TEST=Used it in a follow-up patch.
Change-Id: Ie8d0be98f6b703f4db062fe2f728cd2588347202
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413030
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
USB AO is the internal name for the dedicated charging port on
ThinkPads when in S3 or lower.
AOEN (bit 0) is internal name for enabling this feature while AOCF
(bits 2 and 3) is the configuration field. According to Peter Stuge,
AOCF can be configured in this way:
00 => AC S3 S4 S4 USB on, battery S3 USB on, battery S4 S5 off
11 => AC S3 S4 S4 USB on, battery S3 S4 S5 USB off
10, 01 => equivalent to 00
This commit also adds a new configuration field in the CMOS of the
X220 and the X201 to activate this feature. It probably can be also
added to all the ThinkPads that support this functionality.
With this functionality USB devices are able to negotiate full power
from the dedicated port (usually the yellow one) even in S3.
Tested on a X201 and X220 with an Android smartphone: with this
feature enabled it shows "Charging" when connected during S3, without
it it shows "Charging slowly" (or it doesn't charge at all on the
X201).
For some reasons the "AC only" mode doesn't work, so it has been
disabled.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/17252
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ie1269a4357e2fbd608ad8b7b8262275914730f6e
Reviewed-on: https://chromium-review.googlesource.com/413055
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.
Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.
BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.
Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412854
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 83df672d2c.
It's based on the assumption that the H8 keeps its configuration
during a suspend/resume cycle. User reports indicate that this might
not be true.
Caching the settings in a cbtable entry might be a better approach.
BUG=None
BRANCH=None
TEST=None
Reviewed-on: https://review.coreboot.org/17411
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Ic4ba862ee7068ffe214c2aeaadecb4390a0e0529
Reviewed-on: https://chromium-review.googlesource.com/412045
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Dependencies on EC code should be specified at board level and not here.
We can include the file unconditionally in romstage and let the linker
decide if it's needed.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17123
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ie2d1970ac1dd175a9d42651573a88cd866f19cb9
Reviewed-on: https://chromium-review.googlesource.com/410071
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some user might change some devices. After a suspend this reset
to the (nvram) defaults which breaks the user expectation.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16215
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ifacca35210474ec3db41a53d2ad18f3798b14077
Reviewed-on: https://chromium-review.googlesource.com/407177
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some Chrome OS ECs require a small amount of time after a SPI
transaction to reset their controllers before they can service the next
CS assertion. The kernel and depthcharge have always enforced a 200us
minimum delay for this... coreboot should've done the same.
BRANCH=gru
BUG=chrome-os-partner:58046
TEST=Booted Kevin in recovery mode, confirmed that recovery events got
logged with correct timestamps in eventlog.
Change-Id: I6a7baf7859d5d50e299495d118e7890dcaa2c1b0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/392206
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Kconfig hex values don't need to be in quotes, and should start with
'0x'. If the default value isn't set this way, Kconfig will add the
0x to the start, and the entry can be added unnecessarily to the
defconfig since it's "different" than what was set by the default.
A check for this has been added to the Kconfig lint tool.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16834
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Change-Id: I86f37340682771700011b6285e4b4af41b7e9968
Reviewed-on: https://chromium-review.googlesource.com/391938
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of relying on the mainboards to provide their own LID0
ACPI device, provide the infrastructure so that the mainboards
can signal to the EC ASL code to provide the default lid switch
implementation.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16732
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Change-Id: Ie43b1c4f8522db1245f1f479bfdb685d3066121d
Reviewed-on: https://chromium-review.googlesource.com/390397
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before reading the data provided by EC to the host, ensure that data
ready flag is set. Otherwise, it could result in reading stale/incorrect
data from the data buffer.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is read correctly by host on reef.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16258
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0
Reviewed-on: https://chromium-review.googlesource.com/373732
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the CONFIG_CCACHE variable is NOT set, define the CCACHE variable as
blank on the Chrome EC make command line. This will overrride and
disable the CCACHE variable in the Chrome EC makefile.
BUG=None
BRANCH=None
TEST=None
Change-Id: I9492b3af2d6cb746ec285f0bc00bba019229fa17
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16035
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/368783
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This introduces a CHROMEEC_SOURCE variable used for indicating the CrOS
EC source path, with a fallback to 3rdparty/chromeec.
This allows specifying an external path for the CrOS EC source path.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/15765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I9792c7f21597127a385b961b65a00d44cfa37146
Reviewed-on: https://chromium-review.googlesource.com/363937
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The mainboards which use the Chrome EC duplicate the
same logic in the mainboard smi handler. Provide common
helper functions for those boards to utilize.
BUG=chrome-os-partner:54977
Change-Id: I0d3ad617d211ecbea302114b17ad700b935e24d5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15685
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360845
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In particular, update host_event the original value for MKBP was not
set in ToT.
CQ-DEPEND=CL:353634
BUG=b:27849483
BRANCH=none
TEST=Compile on Samus. Tested in Cyan branch.
Change-Id: I60df65bfd4053207fa90b1c2a8609eec09f3c475
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354040
Some platforms have an RTC provided by the Chrome OS EC. Allow the EC to
implement rtc_get() so that this can be plumbed in.
BUG=chrome-os-partner:52220
BRANCH=none
TEST=(partial) with future commits, boot on gru and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:44
Then reboot ~10 seconds later and see output:
Date: 1970-01-17 (Saturday) Time: 1:42:53
Change-Id: Icaa381d32517dfed8d3b7927495b67a027d5ceea
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351780
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The Chrome OS bootloader is changing its EC software sync mechanism to
look for the hash of an EC image in a separate CBFS file, rather than
using the CBFS hash attribute of the image itself (see
http://crosreview.com/348061). This patch makes coreboot generate
appropriate hash files for the new format when it builds and bundles a
Chrome EC image. This also allows us to compress the EC image itself.
Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/15039
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry-picked from commit 8e97d00755)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/350070
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
